Astera Labs
Principal Physical Design Engineer
- Full-time
... formal verification (equivalence) at the block and full-chip level. - Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production. - Experience with Cadence and/or Synopsys physical design tools/flows. - Familiarity and working knowledge of System Verilog/Verilog. - Experience ...
Ahmedabad, भारत