Vmware
Design analysis engineer
Rs 4 - 8 lakhs p.a.
Job description Block Level and Full chip level Static(IR)/Dynamic(IVD) sign-off Signal/Power EM sign-off at Block level and Full chip Custom power grid implementation for block/hardmacs System level Analysis (PDN) with board, package, interposer and die Work with SoC and packaging team in bump assignment, pkg routing
India, Bengaluru