6 ARS - 9 ARS
Lead RTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 6 to 9 Years 6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Strong Domain Knowledge on RTL Design, implementation, and Timing analysis. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience ...
Chennai, भारत