Anthriq
Senior RTL Design Engineer
Rs 20 - 25 lakhs p.a.
... critical arithmetic paths (carry-save adders, Wallace trees, Booth-encoded multipliers) ● Work with the verification team to achieve per-opcode coverage across all supported data types. Requirements ● 5+ years RTL design in SystemVerilog ● Strong arithmetic unit design (multipliers, dividers, adders — not just instantiating IP) ...
Bangalore, भारत