PQAngels Technologies Pvt. Ltd
RTL Design Engineer
- Full-time
Rs 20 per hour
... candidates with strong hands-on experience in RTL development, Verilog/SystemVerilog, SoC/Subsystem design, NoC, and ASIC design flows . What You Will Work On - Design and develop synthesizable RTL using Verilog/SystemVerilog. - Convert microarchitecture specifications into RTL implementations. - Own block-level RTL design, ...
Bangalore, भारत