Remote Full-time analog layout jobs in Pune, India.

... fifteen times is not an option. At Synopsys, you will work on IO and analog IP that ships in real products, with a team that knows the difference between a layout that works and one that just closes. What You'll Be Doing - Design and own full custom analog layouts for GPIO, specialty IO, and general-purpose analog IP blocks ...

... drive layouts to clean signoff - Collaborate with memory compiler architects and circuit designers to translate specifications into manufacturable, verified layout deliverables - Script layout automation flows using TCL, Perl, or C-shell to improve productivity and ensure consistency across memory variants - Support formal ...

... (FinFET, GAA) to define what is physically possible and translate that into actionable layout guidelines for embedded memory compiler teams - Architect and build layout automation frameworks using Python and TCL that generate, verify, and validate custom memory IP layouts at scale, not one-off scripts but production infrastructure ...

... drive layouts to clean signoff - Collaborate with memory compiler architects and circuit designers to translate specifications into manufacturable, verified layout deliverables - Script layout automation flows using TCL, Perl, or C-shell to improve productivity and ensure consistency across memory variants - Support formal ...

... and next-generation data centers. The problems are hard, the stakes are real, and the team expects you to lead. What You'll Be Doing - Lead complete physical layout development for advanced memory IP including SRAM, ROM, eDRAM, and emerging memory types across nodes from 3nm to mature technologies - Drive layout architecture ...

... and transistor-level implementation for ultra-high-speed, ultra-low-power, or high-density memory configurations - Perform schematic entry, SPICE simulation, layout planning, and supervise physical layout execution through to final verification - Develop and verify bitcells, define layout rules, and drive layout design and ...

... and transistor-level implementation for ultra-high-speed, ultra-low-power, or high-density memory configurations - Perform schematic entry, SPICE simulation, layout planning, and supervise physical layout execution through to final verification - Develop and verify bitcells, define layout rules, and drive layout design and ...

... through tapeout and beyond. You think in tradeoffs. Power versus area, speed versus yield, custom circuit elegance versus compiler automation constraints. When a layout is failing timing or a bit cell is not meeting yield targets at 3nm, you do not panic or wait for more data. You pull the team together, dig into the SPICE decks, ...