Anthriq
Senior RTL Design Engineer
Rs 20 - 25 lakhs p.a.
... dividers, adders — not just instantiating IP) ● IEEE 754 floating-point implementation experience ● Fixed-point arithmetic, saturation modes, rounding modes ● Understanding of pipelining and multi-cycle datapath design ● Comfortable working from a detailed architecture spec Nice to Have ● DSP datapath experience (MAC units, butterfly ...
Bangalore, भारत