Renesas Electronics
Sr Staff Engineer, Design Verification
- On-site
- Full-time
... related discipline. - 6 - 14 years of experience in Digital Verification with Strong expertise in System Verilog, UVM methodology and constrained-random verification. - Experience with Formal Verification techniques and tools to complement simulation-based verification - advantage. - Solid understanding of Computer Architecture, ...
Hyderabad, भारत