Test Engineer I - DFT/FPGA in Hyderabad, India - Jobeax
Vacancy description
Test Engineer I - DFT/FPGA in Hyderabad, India
Tech Grow Global
India, Hyderabad
Test Engineer I - DFT/FPGA in Hyderabad, India is listed on Jobeax. Browse 30,000+ vacancies available.
About the Role:We are looking for a Functional DFT / Test Engineer to join the Test Development team and work on advanced 7nm FPGA/MPSoC products. The role involves developing production test solutions, test methodologies, bring-up sequences, and debugging test patterns across simulation, bench, and ATE https://jobeax.com/link/D97KR0fNczjlIZqw Responsibilities:- Develop production test solutions for complex FPGA/MPSoC products with focus on quality, cost, and diagnosability.- Define and implement test strategies using Verilog RTL and system-level design flows.- Develop and validate IP block bring-up sequences in simulation and ATE environments.- Debug firmware, test patterns, and hardware issues across simulation, bench, and ATE.- Collaborate with IC Design, FPGA Firmware, Verification, Characterization, and Product Test teams.- Support root-cause analysis and timely delivery of robust manufacturing test patterns.- Work with DFT methodologies such as Scan and https://jobeax.com/link/fIRD8rnxGSFK3fsM Skills:- B.E./B.Tech/M.E./M.Tech in Electrical, Electronics, Computer Engineering, IC Design, or equivalent.- 1 - 3 years of experience in embedded/semiconductor/test development.- Good knowledge of Verilog RTL and hardware functional verification.- Strong understanding of semiconductor fundamentals and digital electronics.- Comfortable working in Linux environments.- Scripting knowledge in Perl and/or Tcl.- Strong analytical, debugging, and problem-solving skills.- Good communication and ability to collaborate with global https://jobeax.com/link/826m1CLX72UbjX1R to Have:- Knowledge of DFT, Scan, ATPG, and test methodologies.- FPGA digital design and firmware development experience.- Embedded C programming for processor/microcontroller applications.- Pre-silicon validation and post-silicon debug experience.- Experience with simulation and basic lab/bench equipment. (ref:hirist.tech)
... Type: Full-time We are looking for a skilled FPGA Design Verification Engineer with hands-on experience in the Xilinx Vivado implementation flow to validate and test FPGA implementation stages, including placement and Static Timing Analysis (STA). The ideal candidate will have a strong understanding of FPGA design flows, digital ...
... Type: Full-time We are looking for a skilled FPGA Design Verification Engineer with hands-on experience in the Xilinx Vivado implementation flow to validate and test FPGA implementation stages, including placement and Static Timing Analysis (STA). The ideal candidate will have a strong understanding of FPGA design flows, digital ...
... Type: Full-time We are looking for a skilled FPGA Design Verification Engineer with hands-on experience in the Xilinx Vivado implementation flow to validate and test FPGA implementation stages, including placement and Static Timing Analysis (STA). The ideal candidate will have a strong understanding of FPGA design flows, digital ...
... https://jobeax.com/link/SKciAM5XjIOOw9Ja Skills :- Familiarity with industrystandard DFT tools (e.g., Synopsys DFT, Mentor Tessent).- Knowledge of lowpower design techniques and their impact on testability.- Experience working in crossfunctional ASIC or SoC development https://jobeax.com/link/tbV87hPFdlI3znrY :- Bachelors degree in Electrical Engineering, ...
... https://jobeax.com/link/SKciAM5XjIOOw9Ja Skills :- Familiarity with industrystandard DFT tools (e.g., Synopsys DFT, Mentor Tessent).- Knowledge of lowpower design techniques and their impact on testability.- Experience working in crossfunctional ASIC or SoC development https://jobeax.com/link/tbV87hPFdlI3znrY :- Bachelors degree in Electrical Engineering, ...
Job Overview : We are looking for experienced DFT Engineers to join our VLSI team. The role involves DFT architecture, implementation, verification, and silicon bring-up/debug across various levels of https://jobeax.com/link/NfKu17xn3PQ6gnFL Responsibilities : - Develop and implement Design-for-Test (DFT) architecture and ...
FPGA Design Engineer Hughes Systique Corporation (HSC) , a leading global digital solutions and service provider, is expanding its team in Dehradun, Uttarakhand . This is a great opportunity for FPGA Design Engineers to work on cutting-edge projects with a multinational company—right here in Dehradun. IKSANA is supporting ...
... are seeking a Senior FPGA Verification Engineer with 4–8 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. Drive debug and root-cause analysis of functional issues and work closely with FPGA RTL designers Review FPGA RTL, verification code, and test plans ...
... robustness, and overall performance . - Optimise algorithms for FPGA, GPU, embedded processors, and other hardware acceleration platforms . - Collaborate with FPGA, embedded software, RF, hardware, and systems engineering teams. - Support algorithm integration, system testing, debugging, and performance evaluation. - Participate ...
... LVS, and physical verification issues.- Drive GDSII release readiness and tape-out https://jobeax.com/link/I0qZVEWljaVxivZ2 & Testability :- Define and review DFT architecture including Scan, MBIST, LBIST, and JTAG.- Support ATPG pattern generation and coverage closure.- Collaborate with product engineering and validation ...
... LVS, and physical verification issues.- Drive GDSII release readiness and tape-out https://jobeax.com/link/I0qZVEWljaVxivZ2 & Testability :- Define and review DFT architecture including Scan, MBIST, LBIST, and JTAG.- Support ATPG pattern generation and coverage closure.- Collaborate with product engineering and validation ...
... functionality, performance, and subsystem validation.- Work across Camera, Display, GPU, Memory, Security, and SoC subsystems.- Build reusable frameworks for Pre-Silicon (FPGA/Emulation) and Post-Silicon environments.- Debug embedded software on emulators, FPGA platforms, and silicon development boards.- Support silicon bring-up, subsystem ...
... experienced Test Engineer with hands-on experience in the semiconductor domain and ATE (Automated Test Equipment) . The ideal candidate should have experience in ATE test program development, silicon validation, device characterization, hardware debugging, and wafer/final testing. Experience with Teradyne, Advantest, NI Cohu , ...
... our products perfectly meet our quality, performance, and Fitting requirements. We offer a permanent contract, starting from September 2026. As a Lead Field Test Engineer (FTE), you will drive the Fitting tests validation of Footwear products within our Sports Category. Working in close collaboration with the Production ...
... With more than 3 billion devices shipped, SiTime is changing the timing industry. A Senior Test Development Engineer is responsible for hardware and software test solution development for SiTime's precision timing devices. From the initial product development kick-off until end of life, the ATE Test Development Engineer ...
Location: Hyderabad, TG, IN Application Engineer I Are you ready to shape the future of international insurance through cutting-edge cloud technology? Do you thrive on solving complex technical challenges and building products that make a real difference for clients around the world? If so, we want to hear from you! About ...
... challenges and building products that make a real difference for clients around the world? If so, we want to hear from you! About the Role As an Application Engineer I at Swiss Re, you will be at the heart of building and running industry leading applications that power international insurance programs. Working alongside ...
... problems from occurring in the first place? If so, you are exactly the kind of talent we are looking for. We are seeking a technically curious, interface‑savvy engineer to join our team. The candidate will take ownership of engineering activities spanning development, system integration, and technical analysis within the Subledger ...