Job Description :- 10 years with expertise in full-chip timing closureKey Responsibilities :- Lead full-chip static timing analysis and drive timing signoff for complex SoC designs- Develop advanced timing methodologies incorporating AOCV, POCV, and statistical timing analysis- Mentor timing engineers on advanced STA techniques, debugging strategies, and tool usage- Interface with design, synthesis, and physical implementation teams to resolve timing challenges- Conduct multi-voltage domain analysis and ensure proper timing across voltage level shifters- Establish timing quality metrics and implement continuous improvement initiatives- Evaluate new timing analysis tools and methodologies for improved accuracy and efficiency- Lead timing aspects of design reviews, tapeout readiness assessments, and post-silicon correlation (ref:hirist.tech)
Job Description :- 10 years with expertise in full-chip timing closureKey Responsibilities :- Lead full-chip static timing analysis and drive timing signoff for complex SoC designs- Develop advanced timing methodologies incorporating AOCV, POCV, and statistical timing analysis- Mentor timing engineers on advanced STA techniques, ...
... review floor planning, placement, CTS, power planning/routing, and place & route.- Lead timing closure across complex and performance-critical designs.- Drive Static Timing Analysis and resolve complex setup, hold, congestion, transition, and clock-related issues.- Lead DRC/LVS closure and coordinate with physical verification ...
... review floor planning, placement, CTS, power planning/routing, and place & route.- Lead timing closure across complex and performance-critical designs.- Drive Static Timing Analysis and resolve complex setup, hold, congestion, transition, and clock-related issues.- Lead DRC/LVS closure and coordinate with physical verification ...
... activities for complex blocklevel and toplevel ASIC/SoC designs.- Drive floor planning, placement, CTS, power planning/routing, and place & route.- Execute timing analysis and drive timing closure across critical paths.- Perform Static Timing Analysis (STA) and implement appropriate timing fixes.- Analyze and resolve setup, ...
... activities including floor planning, placement, CTS, power routing, and place & route.- Work on block-level and/or top-level physical implementation.- Perform Static Timing Analysis (STA) and identify timing violations.- Implement timing fixes and optimize designs for performance, area, and power.- Perform and resolve DRC ...
... activities including floor planning, placement, CTS, power routing, and place & route.- Work on block-level and/or top-level physical implementation.- Perform Static Timing Analysis (STA) and identify timing violations.- Implement timing fixes and optimize designs for performance, area, and power.- Perform and resolve DRC ...
Job Description :- 10 years with expertise in full-chip timing closureKey Responsibilities :- Lead full-chip static timing analysis and drive timing signoff for complex SoC designs- Develop advanced timing methodologies incorporating AOCV, POCV, and statistical timing analysis- Mentor timing engineers on advanced STA techniques, ...
... full physical design flow including floorplanning, power grid design, placement, CTS (Clock Tree Synthesis), routing, signal integrity (IR drop / EM), STA (Static Timing Analysis), and physical verification (DRC / LVS).- SoC-Level Physical Design : Own physical implementation and closure activities for complex SoC designs, ...