Static Timing Analysis Lead in Bangalore, India - Jobeax
Vacancy description
Static Timing Analysis Lead in Bangalore, भारत
Career Makers
Full-timeStandard weekly hours
Bangalore, भारत
Job Description :- 10 years with expertise in full-chip timing closureKey Responsibilities :- Lead full-chip static timing analysis and drive timing signoff for complex SoC designs- Develop advanced timing methodologies incorporating AOCV, POCV, and statistical timing analysis- Mentor timing engineers on advanced STA techniques, debugging strategies, and tool usage- Interface with design, synthesis, and physical implementation teams to resolve timing challenges- Conduct multi-voltage domain analysis and ensure proper timing across voltage level shifters- Establish timing quality metrics and implement continuous improvement initiatives- Evaluate new timing analysis tools and methodologies for improved accuracy and efficiency- Lead timing aspects of design reviews, tapeout readiness assessments, and post-silicon correlation (ref:hirist.tech)
... https://jobeax.com/link/B2cR4cnNG1o60XK8 Description :- Ability to handle the complete physical design and analysis of multiple designs independently- Good understanding of the static timing analysis and experience of closing timing requirements on multiple designs- Experience of closing power analysis (IR/EM), equivalency checks as well as ...
... requirements. Discover more at . Tech Lead STA Engineer Location - Hyderabad Experience - 6-14 years Role Overview Astera Labs is hiring a Principal Engineer, Static Timing Analysis to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, ...
... activities including floor planning, placement, CTS, power routing, and place & route.- Work on block-level and/or top-level physical implementation.- Perform Static Timing Analysis (STA) and identify timing violations.- Implement timing fixes and optimize designs for performance, area, and power.- Perform and resolve DRC ...
Job Description :- 10 years with expertise in full-chip timing closureKey Responsibilities :- Lead full-chip static timing analysis and drive timing signoff for complex SoC designs- Develop advanced timing methodologies incorporating AOCV, POCV, and statistical timing analysis- Mentor timing engineers on advanced STA techniques, ...
... full physical design flow including floorplanning, power grid design, placement, CTS (Clock Tree Synthesis), routing, signal integrity (IR drop / EM), STA (Static Timing Analysis), and physical verification (DRC / LVS).- SoC-Level Physical Design : Own physical implementation and closure activities for complex SoC designs, ...
... environments.- Collaborate with ATE and validation teams during silicon/ATE bring-up.- Develop and maintain automation scripts using Perl and TCL.- Support Static Timing Analysis activities where required.- Debug DFT implementation and simulation issues and work with cross-functional teams for https://jobeax.com/link/CQ4wiEZTVhVqdHhK ...
Thermo Fisher Scientific seeks a Technical Lead for Cell Analysis in Bangalore to provide scientific expertise and customer support for flow cytometry, cell sorting, and advanced cell culture technologies. The role combines pre- and post-sales technical consultation, hands-on training, and collaboration with cross-functional ...
... AMBA AXI/AHB/APB - Strong understanding of Static Timing Analysis, synthesis, timing closure, and the ability to make microarchitectural tradeoffs that meet timing and power goals - Hands-on experience with CDC and RDC verification flows, linting, and static sign-off methodologies - Experience with low-power design techniques, ...
... synchronizers, retention, level shifters, power gating, always-on, filler, and decap cells - Debug and resolve correlation issues between characterization results, static timing analysis, and SPICE simulations, working across tool flows to identify root causes - Execute QA checks, regression analysis, and release validation to ...
... timing closure. - Good understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, Calibre, Red Hawk. - Strong understanding of static timing analysis, power analysis, and signal integrity analysis. - Excellent problem-solving skills and attention to detail. - Ability to work effectively in ...