Static Timing Analysis Lead in Bangalore, India - Jobeax
Vacancy description
Static Timing Analysis Lead in Bangalore, भारत
Career Makers
Full-timeStandard weekly hours
Bangalore, भारत
Job Description :- 10 years with expertise in full-chip timing closureKey Responsibilities :- Lead full-chip static timing analysis and drive timing signoff for complex SoC designs- Develop advanced timing methodologies incorporating AOCV, POCV, and statistical timing analysis- Mentor timing engineers on advanced STA techniques, debugging strategies, and tool usage- Interface with design, synthesis, and physical implementation teams to resolve timing challenges- Conduct multi-voltage domain analysis and ensure proper timing across voltage level shifters- Establish timing quality metrics and implement continuous improvement initiatives- Evaluate new timing analysis tools and methodologies for improved accuracy and efficiency- Lead timing aspects of design reviews, tapeout readiness assessments, and post-silicon correlation (ref:hirist.tech)
... activities including floor planning, placement, CTS, power routing, and place & route.- Work on block-level and/or top-level physical implementation.- Perform Static Timing Analysis (STA) and identify timing violations.- Implement timing fixes and optimize designs for performance, area, and power.- Perform and resolve DRC ...
Job Description :- 10 years with expertise in full-chip timing closureKey Responsibilities :- Lead full-chip static timing analysis and drive timing signoff for complex SoC designs- Develop advanced timing methodologies incorporating AOCV, POCV, and statistical timing analysis- Mentor timing engineers on advanced STA techniques, ...
... full physical design flow including floorplanning, power grid design, placement, CTS (Clock Tree Synthesis), routing, signal integrity (IR drop / EM), STA (Static Timing Analysis), and physical verification (DRC / LVS).- SoC-Level Physical Design : Own physical implementation and closure activities for complex SoC designs, ...
Job Description :We are seeking a high-calibre RTL Integration Engineer with 7+ years of experience to lead SoC and subsystem integration for next-generation semiconductor products. You will be responsible for integrating complex internal/third-party IPs, managing bus fabrics, running static quality checks, and collaborating ...
... environment, making sure our food is safe, or helping find cures for cancer. Description: Join our collaborative team at Thermo Fisher Scientific as a Technical Lead, Cell analysis where you will provide world-class scientific expertise and support to our customers in Flow Cytometry and Cell sorting experiments in Basic cell ...
Thermo Fisher Scientific seeks a Technical Lead for Cell Analysis in Bangalore to provide scientific expertise and customer support for flow cytometry, cell sorting, and advanced cell culture technologies. The role combines pre- and post-sales technical consultation, hands-on training, and collaboration with cross-functional ...
... AMBA AXI/AHB/APB - Strong understanding of Static Timing Analysis, synthesis, timing closure, and the ability to make microarchitectural tradeoffs that meet timing and power goals - Hands-on experience with CDC and RDC verification flows, linting, and static sign-off methodologies - Experience with low-power design techniques, ...
... semiconductor design, with direct work in Place & Route, Static Timing Analysis, extraction, and Engineering Change Order flows - Deep technical expertise with timing and physical constraint methodologies, parasitic annotation, and timing analysis for complex IC designs - Proven experience executing silicon chip projects through ...
... PPA solutions to meet the targets. - Good understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC. - Strong understanding of static timing analysis, power analysis, and signal integrity analysis. - Excellent problem-solving skills and attention to detail. - Excellent scripting skills and ...
... AMD/Xilinx Vivado, and Intel Quartus, depending on the evaluation requirements. - Design evaluation scenarios covering synthesis quality, place-and-route outcomes, static timing analysis, timing constraints, and timing closure. - Identify recurring failure patterns in AI-generated designs and translate them into new test cases, ...