Static Timing Analysis Lead in Bengaluru, India - Jobeax
Vacancy description
Static Timing Analysis Lead in Bengaluru, भारत
Career Makers
Bengaluru, भारत
Job Description :- 10 years with expertise in full-chip timing closureKey Responsibilities :- Lead full-chip static timing analysis and drive timing signoff for complex SoC designs- Develop advanced timing methodologies incorporating AOCV, POCV, and statistical timing analysis- Mentor timing engineers on advanced STA techniques, debugging strategies, and tool usage- Interface with design, synthesis, and physical implementation teams to resolve timing challenges- Conduct multi-voltage domain analysis and ensure proper timing across voltage level shifters- Establish timing quality metrics and implement continuous improvement initiatives- Evaluate new timing analysis tools and methodologies for improved accuracy and efficiency- Lead timing aspects of design reviews, tapeout readiness assessments, and post-silicon correlation (ref:hirist.tech)
... associated interfaces.- Drive implementation using AMBA AXI, AHB, and APB protocols.- Review RTL for functionality, performance, area, power, and coding quality.- Lead Lint and CDC analysis, identify violations, and drive closure.- Perform and review ASIC synthesis and Static Timing Analysis (STA).- Analyze timing issues and ...
... activities for complex blocklevel and toplevel ASIC/SoC designs.- Drive floor planning, placement, CTS, power planning/routing, and place & route.- Execute timing analysis and drive timing closure across critical paths.- Perform Static Timing Analysis (STA) and implement appropriate timing fixes.- Analyze and resolve setup, ...
... requirements. Discover more at . Tech Lead STA Engineer Location - Hyderabad Experience - 6-14 years Role Overview Astera Labs is hiring a Principal Engineer, Static Timing Analysis to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, ...
... methodologies.- Good understanding of ARM-based SoC architecture.- Hands-on experience with AMBA AXI, AHB, and APB protocols.- Experience with Lint and CDC analysis.- Understanding of ASIC synthesis and Static Timing Analysis.- Experience with equivalency checking and design quality methodologies.- Exposure to FPGA design ...
... activities including floor planning, placement, CTS, power routing, and place & route.- Work on block-level and/or top-level physical implementation.- Perform Static Timing Analysis (STA) and identify timing violations.- Implement timing fixes and optimize designs for performance, area, and power.- Perform and resolve DRC ...
... Senior STA Engineer with strong expertise in Static Timing Analysis, timing signoff, and timing closure for complex ASIC/SoC designs. The candidate will own timing analysis activities across the design flow and work closely with RTL, Synthesis, Physical Design, and Signoff teams to resolve complex timing issues. Key Responsibilities ...
... Support timing signoff for pre-layout and post-layout stages. - Perform cross-functional reviews for timing convergence and provide recommendations. - Generate timing reports and communicate closure status to project stakeholders. Qualifications - 7–10 years of experience in Static Timing Analysis (STA) and timing closure ...
... environments.- Collaborate with ATE and validation teams during silicon/ATE bring-up.- Develop and maintain automation scripts using Perl and TCL.- Support Static Timing Analysis activities where required.- Debug DFT implementation and simulation issues and work with cross-functional teams for https://jobeax.com/link/CQ4wiEZTVhVqdHhK ...
... and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and execution-focused Static Timing Analysis (STA) engineer with strong fundamentals in timing closure and signoff methodologies. You bring 8+ years of hands-on experience in STA and timing/power ...