Static Timing Analysis Lead in Bengaluru, India - Jobeax
Vacancy description
Static Timing Analysis Lead in Bengaluru, भारत
Career Makers
Bengaluru, भारत
Job Description :- 10 years with expertise in full-chip timing closureKey Responsibilities :- Lead full-chip static timing analysis and drive timing signoff for complex SoC designs- Develop advanced timing methodologies incorporating AOCV, POCV, and statistical timing analysis- Mentor timing engineers on advanced STA techniques, debugging strategies, and tool usage- Interface with design, synthesis, and physical implementation teams to resolve timing challenges- Conduct multi-voltage domain analysis and ensure proper timing across voltage level shifters- Establish timing quality metrics and implement continuous improvement initiatives- Evaluate new timing analysis tools and methodologies for improved accuracy and efficiency- Lead timing aspects of design reviews, tapeout readiness assessments, and post-silicon correlation (ref:hirist.tech)
... constraint issues.- This role will provide SoC and block level timing constraints development exposure.- Responsibilities will include promotion of multiple IP timing constraints to SoC level and integrating them into SoC timing https://jobeax.com/link/oHcnGvlqQTyd2jNh Required : - Understanding of STA concepts and Timing ...
... associated interfaces.- Drive implementation using AMBA AXI, AHB, and APB protocols.- Review RTL for functionality, performance, area, power, and coding quality.- Lead Lint and CDC analysis, identify violations, and drive closure.- Perform and review ASIC synthesis and Static Timing Analysis (STA).- Analyze timing issues and ...
... activities for complex blocklevel and toplevel ASIC/SoC designs.- Drive floor planning, placement, CTS, power planning/routing, and place & route.- Execute timing analysis and drive timing closure across critical paths.- Perform Static Timing Analysis (STA) and implement appropriate timing fixes.- Analyze and resolve setup, ...
... methodologies.- Good understanding of ARM-based SoC architecture.- Hands-on experience with AMBA AXI, AHB, and APB protocols.- Experience with Lint and CDC analysis.- Understanding of ASIC synthesis and Static Timing Analysis.- Experience with equivalency checking and design quality methodologies.- Exposure to FPGA design ...
... Support timing signoff for pre-layout and post-layout stages. - Perform cross-functional reviews for timing convergence and provide recommendations. - Generate timing reports and communicate closure status to project stakeholders. Qualifications - 7–10 years of experience in Static Timing Analysis (STA) and timing closure ...
... environments.- Collaborate with ATE and validation teams during silicon/ATE bring-up.- Develop and maintain automation scripts using Perl and TCL.- Support Static Timing Analysis activities where required.- Debug DFT implementation and simulation issues and work with cross-functional teams for https://jobeax.com/link/CQ4wiEZTVhVqdHhK ...
... and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and execution-focused Static Timing Analysis (STA) engineer with strong fundamentals in timing closure and signoff methodologies. You bring 8+ years of hands-on experience in STA and timing/power ...
... AMBA AXI/AHB/APB - Strong understanding of Static Timing Analysis, synthesis, timing closure, and the ability to make microarchitectural tradeoffs that meet timing and power goals - Hands-on experience with CDC and RDC verification flows, linting, and static sign-off methodologies - Experience with low-power design techniques, ...