STA Engineer - ASIC/SoC Design in Bangalore, India - Jobeax
Vacancy description
STA Engineer - ASIC/SoC Design in Bangalore, भारत
AMBIT SEMICONDUCTORS PRIVATE LIMITED
Bangalore, भारत
Job Description:Total Experience : 4 - 10 yearsJob Description : - 4+ years of STA and timing closure experience on ASIC/SoC designs- Strong expertise in Setup/Hold analysis, MMMC, OCV/AOCV/POCV, CRPR, SI, and timing signoff- Hands-on experience with SDC constraints, timing exception validation, and ECO closure- Proficiency in PrimeTime/Tempus and Tcl scripting- Experience in subsystem/block-level timing signoff and advanced technology nodes- Good understanding of CTS, extraction, IR-drop, crosstalk, low-power (UPF), and physical design impacts on timing (ref:hirist.tech)
ASIC / SoC Design Verification Engineer Company: PQAngels Technologies Pvt. Ltd. Location: Bengaluru Experience: 5 -11 Years Employment Type: Full-Time About the Role PQAngels Technologies is looking for experienced Design Verification Engineers to work on challenging ASIC, SoC, and Subsystem verification projects. We are ...
... Experience with complex ARM-based SoCs.- Experience with high-performance or low-power digital designs.- Exposure to timing optimization, PPA improvement, and design closure.- Experience reviewing RTL architecture and mentoring design engineers.- Familiarity with industry-standard EDA tools and ASIC design flows. (ref:hirist.tech)
Position Summary :We are seeking an experienced and results-driven Design Verification Manager to lead verification activities for complex IP, subsystem, SoC, and ASIC designs. The ideal candidate will possess strong technical expertise in SystemVerilog/UVM-based verification methodologies, SoC integration, AMBA protocols, ...
... years of hands-on experience in RTL Design / ASIC / SoC Design.- Strong proficiency in Verilog/VHDL and RTL coding methodologies.- Good understanding of ARM-based SoC architecture.- Hands-on experience with AMBA AXI, AHB, and APB protocols.- Experience with Lint and CDC analysis.- Understanding of ASIC synthesis and Static ...
Job Title : Senior Physical Design Engineer / LeadExperience : 9-14 YearsLocation : Bangalore / Kochi / Chennai / PuneEmployment Type : Full-timeAbout the Role : Neurealm is seeking an experienced Senior Physical Design Engineer / Lead to drive physical implementation activities for complex ASIC/SoC https://jobeax.com/link/Ed3TrripOdfvyAWA ...
... and verification. - Open to learning, improving flows, and sharing knowledge within the team. The Team You’ll Be A Part Of: You’ll join a team of backend and STA engineers focused on delivering robust timing and power closure solutions for leading silicon designs. The team values technical rigor, collaboration, and continuous ...
... customers, external partners, and executive stakeholders when https://jobeax.com/link/0XodNN5dLVwUz2NN Qualifications :- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.- 10+ years of experience in ASIC/SoC design and development.- Proven experience in complete ...
... Applicants can expect to work with leading global tech companies and be part of teams driving next-generation hardware and software solutions. Role Description : The ASIC Design Verification Engineer – PQAngels will be responsible for verifying complex ASIC designs using industry-standard methodologies and tools. Day-to-day activities ...
... physical design teams - Accelerate adoption of new design flows and tools like P&R-aware synthesis by piloting techniques and sharing learnings across the broader engineering organization What You'll Need - BSEE or MSEE in Electrical Engineering with 12+ years of hands-on experience in ASIC digital design and RTL implementation ...
... Verilog/System Verilog RTL design. - Experience with complete ASIC design cycles from microarchitecture through RTL implementation and silicon bring-up. - Strong understanding of digital design fundamentals, computer architecture, and SoC integration. - Experience with synthesis, lint, CDC/RDC, STA, and RTL sign-off methodologies. ...