SoftPath Technologies - Lead/Senior Physical Design Engineer - RTL/GDSII in Hyderabad, भारत

Role : Senior / Lead Physical Design Engineer (RTL to GDSII)Location : Hyderabad & BangaloreExperience : 6 to 9 YearsNotice : Immediate to 20 DaysRole Overview : We are looking for an experienced Senior / Lead Physical Design Engineer (6 to 9 Years) to handle complete Netlist-to-GDSII implementation and signoff on advanced technology nodes (5nm and 3nm) using Synopsys and Siemens EDA tool https://jobeax.com/link/Ix5MczuGRkMOcnAx Responsibilities : RTL to GDSII Flow & Implementation : - Execute complete physical design flow including Synthesis, Placement, and Routing (P&R) using Synopsys Fusion Compiler.- Perform Block-level and SoC-level Floorplanning, power mesh structuring, and pin planning.- Implement and optimize Clock Tree Synthesis (CTS) for low skew, latency, and dynamic power.- Define and manage design constraints (SDC) across timing, power, area, and design rules to optimize overall PPA (Power, Performance, Area).Signoff & Physical Verification : - Carry out full-chip and block-level Static Timing Analysis (STA) and timing signoff using Synopsys PrimeTime.- Perform accurate parasitic extraction using StarRC.- Drive power integrity, static/dynamic IR-drop, and EM analysis closure using Ansys Redhawk-SC.- Execute comprehensive Physical Verification including DRC, LVS, Antenna, and Density closure using Siemens Calibre on advanced 5nm/3nm process https://jobeax.com/link/T6kgjWn30vk2dMBj Implementation & Automation : - Implement functional and logical ECOs using Formality ECO.- Drive timing ECO generation and closure using Prime Closure.- Develop and enhance Tcl/Perl/Python scripts for automated flow execution and https://jobeax.com/link/o74vS2xLJkjer1AN : - 6 to 9 years of relevant Physical Design experience.- Strong hands-on expertise in Synopsys Fusion Compiler and PrimeTime.- Proven track record on sub-7nm/FinFET process nodes (5nm / 3nm).- Immediate to 15 days joiners preferred. (ref:hirist.tech)