Senior Verification Engineer - ASIC/System Verilog in Bangalore, भारत

Job Description:Senior ASIC verification role requiring 8 - 15 years of hands-on block, subsystem and chip-top https://jobeax.com/link/AFP6NYKWQD4NovU5 incumbent will develop SystemVerilog and UVM environments and tests, work on mixed-signal devices, implement RAL and functional and code coverage, run gate-level simulations across PVT corners and support DFT and ATPG https://jobeax.com/link/Af01HIy7pLUBKLaA Stack & Skills:- Scripting in Perl, Python or Shell- Collaboration with analog and architecture teams- FPGA-based validation, lab bring-up and customer-debug supportKey Responsibilities :- Architect and implement advanced verification environments using SystemVerilog and UVM to ensure comprehensive coverage and bug-free silicon.- Lead the verification of complex mixed-signal blocks, coordinating with analog and digital teams to resolve interface challenges and timing constraints.- Drive the execution of constrained-random verification and formal verification methodologies to identify edge-case failures and improve overall design robustness.- Mentor junior engineers through code reviews and technical guidance, fostering a culture of engineering excellence and continuous improvement within the team.- Collaborate with design architects to translate complex specifications into executable test plans that accelerate the time-to-market for high-performance https://jobeax.com/link/3c6muOQDCC9kZeGj is a full-time work-from-office role in Bengaluru. (ref:hirist.tech)