Senior Staff Verification Engineer, High-Speed Interconnect in Hyderabad, भारत

Category Engineering Hire Type Employee Job ID 19009 Remote Eligible No Date Posted 10.04.2026

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are
You have spent years verifying IP that has to work in real silicon, not just pass regression. You know that closing coverage is not about hitting a number, it is about understanding what you have not tested yet and why that matters. Protocol specs do not intimidate you. You read them, translate them into test plans, and build environments that catch the corner cases three months before tapeout.
You are the person design teams come to when a regression fails at 3 a.m. and no one can figure out why. You open Verdi, trace the transactions, correlate protocol behavior with RTL state, and find the root cause while others are still guessing. UVM is a tool you use well, not a checkbox you tick. You write clean agents, extend sequences without breaking existing tests, and build scoreboards that actually catch bugs.
Mentoring matters to you. When a junior engineer gets stuck on a constrained-random failure, you do not just fix it, you show them how to think through it. You communicate clearly across teams, whether you are explaining a coverage gap to an architect or walking a design lead through a protocol violation. At Synopsys, you will work on high-speed interconnect IP that powers the next generation of AI and compute systems, and what you verify will ship.

• Own end-to-end verification of UCIe, PCIe, or DDR IP blocks, from test planning and environment bring-up through coverage closure and sign-off
• Build and extend UVM testbenches in SystemVerilog, including agents, sequencers, scoreboards, coverage models, and protocol checkers
• Write directed and constrained-random tests that stress protocol compliance, corner cases, and multi-layer interactions
• Debug complex RTL and testbench failures using Synopsys Verdi, including waveform analysis, protocol trace, and transaction-level debug
• Translate protocol specifications into executable test plans, assertions (SVA), and functional coverage models that map to real silicon risk
• Collaborate with design, architecture, and silicon validation teams on bug triage, ECO impact analysis, and bring-up readiness
• Mentor verification engineers on UVM methodology, debug techniques, and protocol understanding, and contribute to design and verification reviews

The Impact You Will Have

• You will close coverage gaps and catch protocol violations that prevent costly respins and silicon failures

• Your testbenches will become the foundation for future IP releases, reused and extended across product generations
• Design teams will ship with confidence because your verification caught the issues that matter before tapeout
• Junior engineers will level up faster because you showed them how to debug like a senior engineer, not just run regressions
• Cross-functional teams will make better decisions because you explained the verification risk clearly and early
• Silicon validation will spend less time debugging because your pre-silicon verification was thorough and well-documented
• The IP you verify will enable high-speed interconnects in AI accelerators, data center chips, and next-generation compute platforms used by customers worldwide

What You'll Need

• 7+ years of hands-on ASIC or SoC design verification experience, with at least 3 years on protocol-heavy IP
• Deep working knowledge of at least one high-speed protocol: PCIe, UCIe, or DDR, with the ability to read specs and build compliant testbenches
• Strong UVM methodology experience, including building agents, writing constrained-random sequences, implementing scoreboards, and closing functional coverage
• Solid SystemVerilog skills, including object-oriented programming, constrained-random stimulus generation, and SystemVerilog Assertions (SVA)
• Proven ability to debug complex failures using Synopsys Verdi or equivalent tools (FSDB, protocol analyzers, transaction-level debug)
• Experience with industry simulators such as VCS, Xcelium, or Questa, and familiarity with regression and coverage tools like URG
• https://jobeax.com/link/2DENLGgQM7whDhaE or https://jobeax.com/link/s1WvHFV9ITSwCkyS in Electronics, VLSI, Electrical Engineering, or related discipline; working knowledge of a second protocol (PCIe, UCIe, DDR, CXL) is a strong plus

Who You Are

• You can open a 500-page protocol spec, find the state machine that matters, and turn it into a test plan and coverage model within a week

• When a regression fails intermittently, you do not rerun it and hope, you reproduce it, trace it in Verdi, and document the root cause for the de sign team
• You write UVM code that other engineers can read and extend six months later without asking you what it does
• You push back when a test plan is too shallow or a coverage model misses a critical scenario, and you do it in a way that moves the conversation forward
• You can explain a protocol violation to a de sign engineer in two sentences, then walk an architect through the same issue at the transaction level without losing the thread
• You treat verification like a product: your environments are maintainable, your tests are reusable, and your documentation helps the next person who touches your code

The Team You'll Be Part Of
Your recruiter will share more about the team structure and mission during the interview process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.