Responsibilities

Design, build, and maintain high-performance C++ software, runtime components, and diagnostic tools for custom silicon and compute platforms.

Build scalable Hardware-in-the-Loop test harnesses, automated regression frameworks, and CI/CD pipelines across firmware, kernel, runtime, and compiler layers.

Drive qualification workflows, automated regression suites, and release-readiness verification across hardware revisions and platform configurations.

Troubleshoot software-to-hardware communication issues, concurrency bugs, and performance bottlenecks across physical lab hardware and emulation environments.

Collaborate with hardware design, silicon validation, compiler, and vehicle platform teams to translate technical specifications into production software.

Develop developer tooling, telemetry monitors, and automated workflows to improve qualification velocity and software reliability.

Requirements

Bachelor’s or master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.

At least 5 years of industry experience.

Strong proficiency in modern C++ and solid knowledge of data structures, algorithms, object-oriented design, and modular architecture.

Experience designing systems software, applying software testing methodologies, or building scalable test automation frameworks.

Hands-on experience with Linux or Unix environments, build systems, Python or Bash scripting, and modern CI/CD and version-control workflows.

Strong analytical and debugging skills with experience diagnosing complex issues across software and system boundaries.

Curiosity and willingness to learn low-level hardware interfacing, embedded systems concepts, or compiler optimizations.

Preferred: experience with Hardware-in-the-Loop setups, automated lab testbeds, embedded test environments, post-silicon validation, System-Level Testing, ASIC bring-up, or diagnostic software development.

Preferred: exposure to Memory-Mapped I/O, device drivers, firmware, POSIX APIs, bare-metal or RTOS environments, PCIe, I2C, SPI, UART, JTAG, DDR, or DMA.

Preferred: familiarity with LLVM, MLIR, or GCC toolchains and frameworks, or experience optimizing runtime performance for machine learning workloads.

Benefits

Hybrid work schedule in Bangalore.

Full-time position.

Eligibility for a discretionary annual bonus program, equity incentive plan, and company benefits program, subject to eligibility requirements.

Senior Software Engineer, Testing

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