About Axiado

Axiado is redefining how AI infrastructure gets secured and managed. Founded in 2019, we’re a fast-growing, well-funded team of over 180 people worldwide, building the Trusted Control/Compute Unit (TCU), a new class of semiconductor that integrates hardware security, real-time platform management, and AI-driven optimization. Our TCU-based Platform Efficiency Controller is shipping hardware that makes AI servers measurably more efficient, more secure, and more reliable, and we’re extending that foundation into a hardware-anchored management fabric that scales from a single board to the whole fleet.

Backed by strong funding and validated by commercial programs with Tier 1 industry leaders, Axiado has earned recognition through numerous industry awards, including the 2026 AI in Cybersecurity Innovation Award from TMCnet, a Diamond award for Zero Trust Solution of the Year at the 2026 Pinnacle Awards, and Gold at the 2026 Cybersecurity Excellence Awards for AI Security Solution, as well as being a finalist for the Start-Up to Watch Award from the Global Semiconductor Alliance. We’re small enough that every person’s work visibly shapes the company, and we look for people who want to build, not just execute. Every employee holds equity, meaning your work directly builds your stake in the company’s future, not just a paycheck. If you want to help define what comes next, let’s talk.

Job Description

Axiado Corporation is seeking a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-package(SiP) in a fast-growing startup environment. This role is designed for a senior technologist who combines deep hands-on expertise with system-level thinking, and who thrives in high-ambiguity, high-impact settings.

You will define and drive high-performance, low-power packaging architectures spanning 2D and RDL based fan-out (2.5D), chiplet-based designs, and heterogeneous integration, leading efforts from early technology path finding through production ramp. You will work closely with foundries, OSATs, substrate suppliers, and internal cross-functional teams to shape both product execution and long-term packaging strategy.

Key Responsibilities

Serve as technical authority for IC and SiP packaging across multiple products and programs.
Own package architecture and technology roadmap, aligned with product, cost, and scalability goals.
Lead chiplet-based packaging strategies, including UCIe, silicon interposers, and advanced RDL.
Perform and guide hands-on package design and physical layout, including critical structures for High-speed SerDes/PHY (PCIe, CXL), LPDDR5, UCIe, and Other multi-gigabit interfaces.
Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes.
Drive SI/PI, thermal, mechanical, and reliability trade-offs at the system and package levels.
Lead external engagement with OSATs, foundries, and key suppliers for technology development and manufacturing readiness.
Influence product roadmap, risk management, and investment decisions through technical insight.
Establish scalable design methodologies, best practices, and reusable packaging flows.

Qualifications

BSEE or MSEE (PhD a plus) in Electrical Engineering, or related field.
Minimum of 10+ years of experience with extensive IC packaging expertise for SoCs, ASICs, or memory products.
Deep hands-on expertise in Flip-Chip BGA (FCBGA) and System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe)
Strong understanding of electrical, mechanical, thermal, and reliability design trade-offs, Advanced packaging materials and substrate technologies, Design-for-Manufacturing (DFM) and yield optimization
Demonstrated ability to operate autonomously, make high-impact decisions, and execute in a startup environment.

Required Experience

Technical leadership of multiple end-to-end packaging programs, from early architecture through high-volume production.
Proven experience with high-speed SerDes package development, including PCIe Gen5, LPDDR5 / LPDDR5X, USB 3.x or 10G interfaces
Experience defining die-to-die and chiplet based RDL/bump architecture.
Direct collaboration with OSATs, foundries, and substrate suppliers for co-development and ramp.
Strong cross-functional leadership across design, product, test, operations, reliability, and customer teams.
Clear understanding of cost, yield, schedule, and risk trade-offs at a product and portfolio level.

Tools & Preferred Skills

Cadence Allegro Package Designer (APD) or equivalent EDA tools.
Strong background in flip-chip BGA package design and layout.
SI/PI expertise preferred, including S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer.
Experience building new packaging methodologies or platforms from scratch.

Additional Information

Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

We are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are.

Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of

qualifications

, merit, and business need.

Senior IC Packaging Engineer

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