Senior DFT Engineer/Manager in Bangalore, भारत

Job Description: DFT Engineer (Senior / Manager)Role: DFT Engineer / LeadLocation: Bangalore, India (Work from office / Hybrid depending on project)Experience: 3 - 15 YearsEmployment Type: Full-Time, PermanentCompany: Our client is an established, specialized semiconductor engineering services firm delivering cutting-edge VLSI and SoC design solutions to global tier-1 chipmakers and fabless giants. Built on nearly a decade of domain expertise and solid financial stability, the organization specializes in end-to-end turnkey DFT execution down to advanced 3nm technology nodes. They offer engineers deep technical ownership across multi-EDA tool ecosystems and full-lifecycle silicon https://jobeax.com/link/pFXduxMRxdPTtt33 Overview:We are looking for an experienced and hands-on DFT Engineer to work on complex SoC designs and advanced technology nodes. In this role, you will handle architecture, insertion, ATPG pattern generation, simulation, timing constraints, and silicon bring-up activities while collaborating with cross-functional https://jobeax.com/link/ZlR3JZToBtLJKlA9 Responsibilities:- Develop and implement SoC-level DFT architecture, including OCC/OPCG insertion, EDT/Compression logic insertion, and clock module handling for scan purposes.- Perform MBIST insertion, Scan insertion, ATPG pattern generation, and validation.- Execute both Zero-Delay and SDF Timing Simulations.- Conduct simulation debugging using GUI mode on industry-standard simulators (VCS, NCSim, or Xcelium).- Work with fault models including Stuck-at, Transition Delay Faults (TDF), and IDDQ, applying scan test coverage improvement techniques.- Provide test-mode timing constraints and handoffs to STA and Physical Design (PD) teams.- Support post-silicon bring-up and/or production activities, including tester debug using shmoo plots and graphs.- Interface with cross-functional and external stakeholder teams; lead and mentor junior DFT https://jobeax.com/link/Ty0L1iiUuLw7S9Mr & Technical Skills:- Domain Knowledge: Clear conceptual and practical understanding of BSCAN, MBIST, SCAN, ATPG, and simulation methodologies.- Tool Expertise: Practical experience in at least one tool ecosystem:1. Siemens (Tessent)2. Synopsys3. Cadence- Simulators: Hands-on debugging experience with VCS, NCSim, or Xcelium.- SoC & Flow Exposure: Proven background in digital ASIC/VLSI execution flows, timing closure interaction (STA/PD), and compression architecture.- Background & Stability: Minimum 2 years of tenure in previous organizations.- Education: B.E. / https://jobeax.com/link/2DENLGgQM7whDhaE / M.E. / https://jobeax.com/link/s1WvHFV9ITSwCkyS in Electronics & Communication, Electrical, VLSI, Microelectronics, or related engineering fields.- Notice Period: Immediate to 60 days. (ref:hirist.tech)