Vacancy description
Intel Corporation
India, Bengaluru
Senior Design & Analysis Engineer in Bengaluru, India is listed on Jobeax. Browse 30,000+ vacancies available.
As an IP Logic Design Engineer, you will play a pivotal role in developing high-quality intellectual property (IP) for Unified Intel Chassis designs. This position is at the forefront of Intel's innovation, ensuring that our products consistently deliver world-class performance, power efficiency, and reliability. Work closely with architects to define and design complex protocol bridges. Own privilege qualification and policy propagation across AXI-Lite, APB, IOSF-SB, and HBW request paths. Design and validate parity/ECC generation and checking for request, response, and data channels. Build or integrate logging, interrupt, and firmware-visible error harvesting flows for local and global RAS handling. Own debug and trace data paths for wrapper-level and fabric-level observability, including data capture, transport, formatting, and handoff to downstream debug infrastructure. Design counters, sticky status, snapshots, and firmware-visible CSRs that make performance and failure analysis practical. Support root-cause analysis of bandwidth loss, latency outliers, protocol stalls, and intermittent field or lab issues using hardware observability features.
Develop logic designs, register transfer level (RTL) coding, and simulations required for IP blocks, functional units, and subsystems.
Apply strategies, tools, and methods to optimize RTL design for power, performance, area, and timing targets.
Experience with secure MMIO, access-control/firewall logic, or privilege-based filtering.
Experience with RAS concepts such as fault containment, poison, interrupt generation, logging, and recovery-oriented design.
Drive compliance with quality assurance standards to enable smooth IP handoff within the SoC development process.
Bachelor's degree in electrical engineering, Computer Engineering, or related field.
A minimum of 8 years of experience in logic design and RTL development.
Proficiency in hardware description languages such as Verilog, System Verilog.
Strong understanding of digital design principles, including timing analysis, power optimization, and area trade-offs.
Experience with industry-standard EDA tools for design and simulation (e.g., Master's or PhD degree in Electrical Engineering, Computer Engineering, or related field.
Experienced Hire
Shift
Shift 1 (India)
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment.
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