PQAngels Technologies is looking for experienced RTL Design Engineers to join our semiconductor/VLSI engineering team.
We are looking for candidates with strong hands-on experience in RTL development, Verilog/SystemVerilog, SoC/Subsystem design, NoC, and ASIC design flows .
What You Will Work On
Design and develop synthesizable RTL using Verilog/SystemVerilog.
Convert microarchitecture specifications into RTL implementations.
Own block-level RTL design, development, and debugging.
Work on SoC/Subsystem and NoC-based designs .
Perform RTL quality checks, including Lint and CDC .
Support synthesis and resolve synthesis-related issues.
Collaborate with DV, Physical Design, and SoC Integration teams .
Analyze and optimize designs for Performance, Power, and Area (PPA) .
Participate in design reviews and technical discussions.
Support customer-facing technical discussions when required.
Requirements
Key Skills
Must Have:
Verilog
SystemVerilog
RTL Design
Microarchitecture
ASIC/VLSI Design Flow
Synthesis
Lint & CDC
RTL Debugging
Good to Have:
NoC / Subsystem
CPU / GPU architecture
DDR
PCIe
USB
Ethernet
TCL / Python / Perl scripting
Tools
Synopsys Design Compiler
SpyGlass
VC SpyGlass
Benefits
Why PQAngels?
Work on advanced Semiconductor / ASIC / VLSI projects
Exposure to IP, Subsystem and SoC verification
Opportunity to work with experienced semiconductor engineers
Exposure to global projects and customers
Strong technical learning and career-growth opportunities
Physical Design EngineerNeurealm is looking for a skilled Physical Design Engineer with hands-on experience across the physical implementation flow for ASIC/SoC designs. The ideal candidate should have practical experience in floor planning, placement, CTS, routing, timing closure, and physical verification, along with ...
... RTL and Embedded Processor Application. Test and debug the silicon on board with the help of lab equipment and protocol testers. Typical day for Validation Engineer would include following activities:- Validation design creation using our FPGA design flow- RTL and Embedded C based test design development- Validation of ...
... synthesizable design practice. - Familiarity with simulation debug; lint, CDC, or synthesis exposure is a plus. - Scripting (Python, TCL, Perl) and AI-assisted design tools are a plus. Who You Are: - A strong RTL engineer with quality mindeset who finishes what they own. - Responsive in reviews and debug. - Curious about protocol ...
... compliance for seamless IP and SoC handoff throughout the design https://jobeax.com/link/5JZZMDxlqWRggzCl Qualifications : - Bachelor's or Masters/Phd in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 3+ years of experience.- Expertise in microarchitecture, RTL design, coding, and simulation ...
Job Title : Senior Physical Design EngineerLocation : Ahmedabad, GujaratCompany : VeriFast TechnologiesAbout the Role : VeriFast Technologies is looking for an experienced Physical Design Engineer with 7+ years of hands-on experience in ASIC/SoC physical implementation and RTL-to-GDS (RT2GDS) https://jobeax.com/link/IaPZxBOe81ntp76v ...
... remote within India and is suited to engineers who enjoy solving complex technical problems, automating workflows, and pushing the boundaries of AI-driven chip design. Accountabilities: - Develop realistic engineering evaluation tasks spanning RTL design, functional verification, logic synthesis, physical design, and sign-off. ...
Design Verification Engineer : Experience : 5 - 8 YearsLocation : Bangalore / Kochi / Chennai / PuneJob Type : Full-timeAbout the Role : We are looking for a skilled Design Verification Engineer with hands-on experience in live semiconductor/SoC verification projects. The ideal candidate should have strong expertise in ...
Design Verification Engineer : Experience : 5 - 8 YearsLocation : Bangalore / Kochi / Chennai / PuneJob Type : Full-timeAbout the Role : We are looking for a skilled Design Verification Engineer with hands-on experience in live semiconductor/SoC verification projects. The ideal candidate should have strong expertise in ...
... objectives. - Verify functionality of designs involving high-speed protocols, particularly PCI/PCIe and USB . - Debug simulation failures and collaborate with RTL design engineers to identify and resolve functional issues. - Analyze functional and code coverage and drive verification toward closure. - Participate in design and ...
... Power Management ICs/Analog intensive ICs. - Must have experience of defining the micro-architectures and sub-blocks for the ICs to ensure optimized Digital design, RTL design and Gate level netlist etc. - Must be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner - ...