Principal/Lead Physical Design Engineer - ASIC/SoC in Chennai, भारत

Role : Principal / Lead Physical Design EngineerNeurealm is looking for a highly experienced Principal / Lead Physical Design Engineer to provide technical leadership across complex ASIC/SoC physical implementation https://jobeax.com/link/UDDBmMi9Ox2qFdi5 role involves ownership of physical design architecture and methodology, driving implementation and sign-off, resolving complex timing and physical verification challenges, and providing technical mentorship to senior and junior https://jobeax.com/link/D2R7aDvMFh9bTP8V Responsibilities : - Provide technical leadership for the complete physical design and implementation flow from netlist to sign-off.- Own physical implementation of complex block-level and top-level ASIC/SoC designs.- Drive and review floor planning, placement, CTS, power planning/routing, and place & route.- Lead timing closure across complex and performance-critical designs.- Drive Static Timing Analysis and resolve complex setup, hold, congestion, transition, and clock-related issues.- Lead DRC/LVS closure and coordinate with physical verification teams.- Optimize designs for performance, power, area, and manufacturability.- Provide technical direction on physical implementation for advanced technology nodes, including 14nm and below.- Lead implementation using tools such as Cadence Innovus and Tempus.- Define and improve physical design methodologies, flows, and sign-off practices.- Identify technical risks early in the implementation cycle and drive mitigation plans.- Lead debugging and root-cause analysis of complex physical design and timing issues.- Collaborate with RTL design, architecture, synthesis, STA, verification, and physical verification teams.- Review physical design strategies, implementation plans, timing reports, and sign-off criteria.- Mentor senior and junior engineers and establish best practices across the physical design team.- Support technical estimation, project planning, resource allocation, and milestone execution.- Drive continuous improvements in physical design automation, productivity, and quality.- Take ownership of designs where a predefined/customer-specific flow may not be available and establish the required implementation https://jobeax.com/link/kYzRGmqlbSFQ2qQm Skills : - 15 - 18 years of strong experience in Physical Design / ASIC Implementation.- Expert-level knowledge of Floor planning, Placement, Clock Tree Synthesis, Power planning/routing, Place & Route, Timing closure, and DRC/LVS.- Expert knowledge of Static Timing Analysis and timing closure methodologies.- Strong hands-on experience with Innovus and Tempus.- Deep understanding of advanced-node physical design, preferably 14nm or below.- Strong understanding of physical verification and ASIC sign-off methodologies.- Proven ability to independently lead complex physical implementation programs.- Strong expertise in PPA optimization and design closure.- Excellent debugging and problem-solving capabilities.- Proven experience mentoring engineers and providing technical leadership.- Strong cross-functional communication and stakeholder management https://jobeax.com/link/Cexs453KRiH2S1rJ Skills : - Experience with complex SoC, CPU, or high-performance ASIC designs.- Experience establishing physical design flows for new projects.- Previous experience working on designs without a customer-specific flow.- Experience in methodology development, automation, and flow optimization.- Strong understanding of advanced-node design challenges and sign-off requirements. (ref:hirist.tech)