Makonis software Solutions - DFT Staff Engineer in Bangalore, भारत

DFT Staff EngineerTotal Positions: 10Exp range: 08 - 12 YrsLocation: Bangalore & HyderabadNotice Period: ImmediateSkill:DFT (Design for Test) is a specialized domain in the semiconductor/VLSI industry that ensures integrated circuits (ASICs/SoCs) are testable during manufacturing. DFT engineers design and implement test structures such as Scan, ATPG, MBIST, LBIST, and JTAG to improve chip quality, fault coverage, and manufacturing https://jobeax.com/link/t76L6q1DCYzFPqbb skills to target:- End-to-end DFT implementation- Scan insertion & compression, ATPG- MBIST, LBIST, JTAG/Boundary Scan- DFT signoff, fault coverage, debugging- RTL, SoC design flow, STATools: Siemens Tessent, Synopsys TestMAX, Cadence ModusScripting: TCL, Python, PerlA DFT Staff Engineer is responsible for designing, implementing, and signing off Design-for-Test (DFT) architecture for complex SoCs/IPs. The role ensures that semiconductor designs are testable, high-quality, and manufacturable, while balancing coverage, performance, power, and https://jobeax.com/link/K8alYFAPyzvLdvNZ Responsibilities:DFT Architecture & Strategy:- Define and implement DFT architecture at block/IP or SoC level- Specify test methodologies (scan, MBIST, boundary scan, compression)- Ensure testability built early into RTL design flow- Balance trade-offs between coverage, area, power, and test timeDFT Implementation:- Scan insertion and stitching- ATPG pattern generation and simulation- MBIST / LBIST / boundary scan integration- Develop and validate DFT timing constraints (STA)- Execute DFT flows at RTL and gate levelTest Coverage & Quality :- Analyze and improve fault coverage- Debug scan/ATPG issues and resolve coverage holesOptimize :- Pattern count, test cost, and test timeVerification & Signoff :- Run DFT verification and DRC checks- Ensure clean DFT signoff (coverage, timing, power impact)- Validate patterns using simulation and test tools- Support DFT integration guidelines at SoC levelCross-Functional Collaboration :- Work with RTL design, Physical design (PD), Verification, and Test engineering / ATE teams- Drive issue resolution across teams- Ensure end-to-end execution of DFT flowsSilicon Bring-up & Debug :- Support post-silicon debug and yield improvement- Debug tester failures and improve manufacturing coverage- Assist customer or product teams during bring-upQualifications :- BSEE/MSEE (or equivalent)- Typically 7+ years of DFT / ASIC experience (Staff-level expectation)- Proven experience in end-to-end DFT implementation and debugging (ref:hirist.tech)