HCL - SoC Architect in Hyderabad, भारत

Are you passionate about defining the architecture of next-generation semiconductor products?Join our team as a SoC Architect and drive the end-to-end architectural vision for complex SoCs, from specification and partitioning to implementation, tapeout, and silicon https://jobeax.com/link/Rai3FP7OIupXXKkD Overview :As a SoC Architect, you will own the system-level architecture of the chip, defining subsystem boundaries, memory hierarchy, interconnect topology, power strategy, and performance targets. You will be the technical leader responsible for balancing performance, power, area, cost, and schedule tradeoffs while working closely with cross-functional engineering https://jobeax.com/link/ZlR3JZToBtLJKlA9 Responsibilities :- Define and own SoC architecture, subsystem partitioning, memory hierarchy, NoC/bus architecture, and power/clock domains.- Drive architectural tradeoff decisions across performance, power, area (PPA), cost, and schedule.- Lead architecture reviews, sign-off milestones, and technical decision-making across Design, Verification, DFT, Physical Design, Firmware, and Product teams.- Own area, power, timing, and cost budgeting across all SoC subsystems.- Define IP sourcing strategy, reuse methodology, integration architecture, and interface specifications.- Act as the primary technical escalation point for architecture and implementation challenges.- Collaborate with stakeholders to translate product requirements into scalable silicon https://jobeax.com/link/qVQYcn8zRo6FsrUo Qualifications :- M.S./Ph.D. in Electrical Engineering, Computer Engineering, or equivalent experience.- 10+ years of experience in ASIC/SoC development with significant architecture ownership.- Proven track record of leading full-chip architecture or major subsystem architecture for successful silicon products.- Strong expertise in :1. SoC Architecture2. NoC / Interconnect Design3. Memory & Cache Hierarchies4. Low-Power Design & DVFS5. Physical Design Constraints6. PPA Optimization7. IP Integration & Reuse Strategies8. System-Level Performance ModelingPreferred Experience :- Advanced process nodes and multi-generation SoC development.- Mobile, Automotive, Data Center, Networking, AI/ML, or Edge Computing products.- Hardware-Software Co-design and Firmware Architecture.- Performance, Power, and Architectural Modeling https://jobeax.com/link/wwxDV38QVPu6NLjl :Bangalore/Chennai/Hyderabad/KochiIf you're interested in shaping next-generation silicon products and leading critical architectural decisions, we'd love to connect. (ref:hirist.tech)