Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering
Job Description:
We are seeking a skilled and detail-oriented Functional Verification Engineer to be part of our IP/SoC verification team. The candidate will be responsible for verifying complex digital designs using industry-standard methodologies to ensure functional correctness and high-quality silicon delivery.
Key Responsibilities:
Develop and execute verification test plans based on design specifications and architecture.
Design and implement testbenches using SystemVerilog and UVM methodology.
Create constrained-random and directed test cases.
... designers Review FPGA RTL, verification code, and test plans to ensure quality and completeness Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field Experience: 4–8 years of hands-on experience in functional verification Experience with hardware/software co-verification High attention ...
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... a top engineering institute.- 5+ years of hands-on experience in ASIC/SoC verification.- Strong proficiency in SystemVerilog, UVM, and constrained-random verification methodologies.- Solid understanding of digital design, RTL coding (Verilog/VHDL), and simulation flows.- Proven debugging experience in complex hardware/software ...
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... functional and performance targets Bachelor's or Master's degree in Electronics Engineering, Computer Engineering. - 8+ years of experience in ASIC or FPGA design verification. - Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as System Verilog. - Strong hands-on ...
... engineering teams throughout the verification lifecycle. - Participate in design and verification reviews and contribute technical recommendations. - Maintain verification documentation, test plans, environments, results, and closure reports. - Mentor junior verification engineers and contribute to verification best practices ...