Hardware Design Engineer II - Static Timing Analysis in Bengaluru, भारत

WE ARE HIRING | Hardware Design Engineer IIBangaloreExperience : 3 to 6 YearsWe are looking for a Hardware Design Engineer II with strong expertise in STA concepts and timing constraint https://jobeax.com/link/GEhg53nua6LJMZnl Duties : - Must have solid understanding of timing constraints and their verification at SoC and block level along with good understanding of STA concepts to debug timing constraint issues.- This role will provide SoC and block level timing constraints development exposure.- Responsibilities will include promotion of multiple IP timing constraints to SoC level and integrating them into SoC timing https://jobeax.com/link/oHcnGvlqQTyd2jNh Required : - Understanding of STA concepts and Timing constraints as well as VLSI design flow.- Familiarity with Verilog, timing (.lib), LEF, GDS.- Familiarity with physical design verification, e.g. DRC and LVS.- Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related https://jobeax.com/link/fD8Ur5T2Fb4vICay Have : - Hands-on timing constraint management for large/SOC-level designs.- Strong STA concepts, debugging skills, and good communication.- SOC-level experience preferred; strong subsystem-level experience can be considered.- Exposure to multiple clocks and modes is https://jobeax.com/link/cbURRKTuc7uRz0xQ : - PrimeTime, TCM, GCA, Fusion https://jobeax.com/link/eT2aTEZNy3raOL5E Required : - Power sequencing and reset blocking https://jobeax.com/link/UjUMx2iVDrmPDrl1 : - Priority should be given to candidates with genuine hands-on SOC/subsystem timing-constraint experience rather than candidates with only standard PD-flow exposure. (ref:hirist.tech)