FPGA Engineer - Chip Design in भारत

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for an FPGA Engineer - Chip Design based in India. The FPGA Engineer - Chip Design will combine advanced semiconductor engineering expertise with the development of technical evaluations for AI systems. In this role, you will design realistic chip-design challenges, develop reference implementations, and assess AI-generated hardware designs against industry standards. You will work across the digital design lifecycle, from RTL development and functional verification to synthesis, physical implementation, and timing closure. Your technical judgment will help identify design weaknesses, verification gaps, and power, performance, and area (PPA) optimization opportunities. Working with engineering and research teams, you will contribute to the development of robust evaluation environments and increasingly sophisticated technical benchmarks. This position offers an opportunity to apply practical ASIC and FPGA design experience to emerging AI technologies and advanced engineering workflows. The role is fully remote within India and is suited to engineers who enjoy solving complex technical problems, automating workflows, and pushing the boundaries of AI-driven chip design. Accountabilities: - Develop realistic engineering evaluation tasks spanning RTL design, functional verification, logic synthesis, physical design, and sign-off. - Create high-quality reference implementations using Verilog, SystemVerilog, or VHDL, supported by testbenches, design constraints, expected outputs, and validation procedures. - Establish clear grading criteria and assessment methodologies that reflect industry-standard chip-design practices and engineering expectations. - Evaluate AI-generated RTL code, testbenches, hardware designs, and implementation results to identify functional errors, architectural weaknesses, and design inefficiencies. - Diagnose verification failures, coverage gaps, timing violations, and suboptimal power, performance, and area (PPA) trade-offs. - Assess hardware designs based on functional correctness, timing requirements, resource utilization, implementation quality, and overall design robustness.

- Configure, maintain, and improve electronic design automation (EDA) environments that enable AI agents to execute realistic chip-design workflows. - Apply relevant industry tools and workflows, including Synopsys, Cadence, Siemens, AMD/Xilinx Vivado, and Intel Quartus, depending on the evaluation requirements. - Design evaluation scenarios covering synthesis quality, place-and-route outcomes, static timing analysis, timing constraints, and timing closure. - Identify recurring failure patterns in AI-generated designs and translate them into new test cases, evaluation scenarios, and more challenging engineering benchmarks. - Collaborate with engineering and research teams to improve evaluation frameworks, testing strategies, technical benchmarks, and overall assessment quality. - Automate design workflows, testing procedures, and results analysis using scripting languages such as Python, Tcl, or Perl. - Document reference designs, engineering assumptions, known failure cases, evaluation criteria, and methodologies to ensure reproducibility and consistency. Requirements: - Have at least 3 years of relevant professional experience, with approximately 3–5 years of hands-on ASIC or FPGA design experience preferred, ideally covering multiple stages of the digital design lifecycle. - Hold a B. E. , B. Tech, or M. Tech degree in Electrical Engineering, Electronics Engineering, VLSI, or a related technical discipline. - Demonstrate strong RTL development skills in Verilog, SystemVerilog, or VHDL, with the ability to develop reliable, maintainable, and functionally correct hardware designs.