The Lead Hardware/ System Design Engineer will participate with the engineering team in the design, development, and implementation of engineering projects. This role requires a fair understanding of engineering principles and the ability to apply them in practical scenarios. The Engineer will work under the guidance of senior engineers and managers to contribute to the successful completion of projects.
The successful candidate will contribute to the development of Image Processing products within the IX R&D team. These products perform real time video and image processing and compositing for display on LED, projection and other displays. The products are part of highly visible systems in environments such as corporate events, rock concerts, television studios, House of Worship, Trade shows and fixed installations. The candidate will take responsibility for the quality completion of designated features and design suitable solutions to complex problems while working as a member of the Image Processing R&D team.
General Job Responsibilities:
Contribute in the design and development of engineering projects.
Prepare detailed technical documentation and reports.
Collaborate with cross-functional teams to ensure project alignment.
Participate in project meetings, providing updates and insights on assigned tasks.
Perform rigorous testing and analysis to ensure project quality and compliance.
Detail Job Responsibilities and Requirements
Expert in Large Logic design:
HDL design language experience: Verilog/ System Verilog.
Design and code modules for reuse.
Good coding style practices: formatting, comments, variable names, etc
Expert in debug:
Identify/Locate potential problems in a large design.
Cross discipline communication
Communicate well with other disciplines: software, product owner, test...
Simulation
Modelsim/ Questasim experience preferred.
Designer test bench for their design.
Scripting
Experience with scripting languages like Python.
Good to have :
Debug problems using Chip-Scope or equivalent .
FPGA undestanding
Undestanidng of C/C++ code
Experience with Xilinx and or Altera design environments.
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