DFT Engineer - ATPG/MBIST in Bangalore, भारत

DFT EngineerExperience : 5 - 8 YearsLocation : Bangalore / Kochi / Chennai / PuneJob Type : Full-timeAbout the Role : We are looking for a skilled Design for Testability (DFT) Engineer with hands-on experience in scan insertion, ATPG, MBIST, DFT simulation, and coverage analysis. The ideal candidate should have practical experience working on RTL and netlist-based DFT flows and strong scripting https://jobeax.com/link/2XqJXLBONIZPT2f1 Responsibilities : - Perform Scan insertion and generate ATPG patterns for Stuck-At and At-Speed faults.- Analyze scan coverage and implement techniques to improve test coverage.- Perform MBIST insertion and simulation for memory testing.- Work on Boundary Scan, TAP Controller insertion, and IEEE 1500/P1500 architectures.- Execute DFT insertion flows at both RTL and netlist levels.- Perform DFT simulations with and without SDF annotation.- Work with synthesis and formal verification tools as part of the DFT implementation flow.- Support DC characterization and related test requirements.- Generate Test Description Language (TDL) for ATE environments.- Collaborate with ATE and validation teams during silicon/ATE bring-up.- Develop and maintain automation scripts using Perl and TCL.- Support Static Timing Analysis activities where required.- Debug DFT implementation and simulation issues and work with cross-functional teams for https://jobeax.com/link/CQ4wiEZTVhVqdHhK Stack : - Tools : Mentor/Siemens EDA, Synopsys, Cadence- Scripting : Perl, TCLRequired Skills : - 5 - 8 years of hands-on experience in DFT / Design for Test.- Strong experience in Scan insertion and ATPG.- Experience with Stuck-At and At-Speed fault models.- Hands-on experience with scan coverage analysis and improvement.- Experience in MBIST insertion and simulation.- Knowledge of Boundary Scan, TAP Controller, and IEEE 1500/P1500.- Experience with RTL and netlist-based DFT insertion flows.- Experience with DFT simulation with and without SDF.- Good knowledge of synthesis and formal verification flows.- Strong scripting skills in Perl and TCL.- Exposure to DFT tools from Mentor/Siemens EDA, Synopsys, and/or Cadence.- Good debugging and problem-solving https://jobeax.com/link/Cexs453KRiH2S1rJ Skills : - Experience with Static Timing Analysis.- Experience with ATE pattern generation and silicon bring-up.- Knowledge of DC characterization.- Exposure to advanced SoC/ASIC DFT flows (ref:hirist.tech)