Design Verification Engineer in Bangalore, भारत

Design Verification Engineer

Company: PQAngels Technologies Pvt. Ltd.

PQAngels Technologies is looking for an experienced Design Verification Engineer to join our VLSI/semiconductor engineering team. The ideal candidate will have strong hands-on experience in SystemVerilog, UVM, Verilog, functional verification, testbench development, and RTL debugging .

The candidate will be responsible for developing and executing comprehensive verification strategies for complex digital designs and ensuring high-quality, robust, and functionally correct silicon-ready designs.

Key Responsibilities

• Develop and maintain reusable SystemVerilog/UVM-based verification environments .
  

• Develop verification plans, test scenarios, test cases, and test sequences based on design specifications.
  

• Build and maintain UVM components including agents, drivers, monitors, sequencers, scoreboards, and reference models .
  

• Develop functional and directed tests to verify RTL design functionality.
  

• Perform functional coverage and code coverage analysis and identify coverage gaps.
  

• Write and debug SystemVerilog Assertions (SVA) .
  

• Perform RTL simulation and debug functional failures using industry-standard simulation tools.
  

• Analyze simulation logs, waveforms, and test failures to identify and resolve verification issues.
  

• Work closely with RTL Design, Architecture, Physical Design, and other engineering teams to resolve design and verification issues.
  

• Verify industry-standard protocols such as AXI, AHB, APB, PCIe , DDR , Ethernet , USB or other relevant interfaces .
  

• Contribute to verification methodology improvements, automation, and reusable verification components.
  

• Participate in design reviews, verification reviews, bug reviews, and technical discussions.
  

• Track verification progress and report coverage, defects, and verification status.
  

• Ensure verification activities are completed according to project milestones and quality requirements.
  

Required Technical Skills

• Strong knowledge of Verilog and SystemVerilog .
  

• Hands-on experience with UVM .
  

• Good understanding of Digital Design and RTL concepts .
  

• Experience in developing UVM testbenches and verification components.
  

• Strong understanding of functional verification methodologies .
  

• Experience with functional coverage and code coverage .
  

• Knowledge of SystemVerilog Assertions (SVA) .
  

• Strong RTL simulation and debugging skills.
  

• Experience with waveform analysis and failure debug.
  

• Knowledge of one or more protocols such as AXI, AHB, APB, PCIe, or AMBA .
  

• Familiarity with simulation and verification tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa/ModelSim , or equivalent tools.
  

• Good understanding of verification planning, regression testing, and coverage closure.
  

• Strong analytical, debugging, and problem-solving skills.
  

Preferred Skills

• Experience in IP, SoC, ASIC, or semiconductor product verification.
  

• Exposure to Python, Perl, Tcl, or scripting for verification automation.
  

• Experience with constrained-random verification.
  

• Knowledge of formal verification concepts is an added advantage.
  

• Experience working with complex SoC/IP blocks and industry-standard protocols.
  

• Familiarity with Git or other version-control systems.
  

• Experience working in an Agile or collaborative semiconductor development environment.
  

Education

• Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering, VLSI, Microelectronics , or a related technical discipline.
  

Experience

• 4+ years of relevant experience in Design Verification / Functional Verification .
  

• Candidates with strong hands-on experience in SystemVerilog and UVM are preferred.
  

Candidate Profile

We are looking for candidates who are technically strong, detail-oriented, and passionate about semiconductor/VLSI verification. The candidate should be comfortable working with cross-functional engineering teams and independently debugging complex verification issues.

Location

Bengaluru, India

Employment Type

Full Time

Note

The selected candidate may be deployed to a client location/project environment based on business and project requirements.

Requirements

• 4+ years of relevant experience in Design Verification / Functional Verification.
  

• Strong hands-on experience in SystemVerilog and UVM.
  

• Strong knowledge of Verilog and digital design/RTL concepts.
  

• Experience developing UVM-based verification environments.
  

• Experience with functional coverage, code coverage, assertions, and coverage closure.
  

• Strong debugging skills using simulation logs and waveforms.
  

• Knowledge of SystemVerilog Assertions (SVA).
  

• Experience with AXI/AHB/APB/AMBA/PCIe or similar protocols is preferred.
  

• Experience with VCS, Xcelium, Questa/ModelSim, or equivalent simulation tools.
  

• Good scripting/programming knowledge in Python, Perl, Tcl, or similar languages is an advantage.
  

• Bachelor's/Master's degree in ECE, Electrical Engineering, VLSI, Microelectronics, or related field.
  

• Strong analytical, communication, teamwork, and problem-solving skills.
  

Benefits

• Opportunity to work on challenging VLSI and semiconductor projects.
  

• Exposure to advanced Design Verification methodologies and technologies.
  

• Opportunity to work with experienced semiconductor engineering teams.
  

• Professional growth and technical learning opportunities.
  

• Collaborative and technology-driven work environment.
  

• Opportunities to work on client-facing semiconductor projects.
  

• Competitive compensation based on experience and technical expertise.