Alternate Job Titles

Constraints Verification Applications Engineer
SDC Flow Application Engineer
ASIC Constraints AE
Timing Constraints Applications Engineer
Design Constraints Methodology Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years living in the space between design intent and what actually gets constrained, and you know that bad SDC is the silent killer of chip schedules. You have seen projects stall because constraints were incomplete, over-constrained, or just plain wrong, and you have learned that getting the constraint flow right early is what separates a clean tapeout from months of painful debug.

You are comfortable sitting with a design team, looking at their RTL, their clock architecture, and their constraint files, and spotting the gaps before they become timing closure nightmares. You do not just write SDC, you understand the methodology behind constraint generation, verification, and management across the entire flow from RTL to signoff. You know when a multi-mode, multi-corner setup is incomplete, and you can explain why it matters without making it sound like a lecture.

Working across R&D, field teams, and customer sites does not intimidate you. You have learned that the best constraint flows come from understanding what the design is actually trying to do, not just mechanically translating specs into SDC. At Synopsys, you will work with semiconductor companies solving real constraint challenges on chips that will ship, and the methodologies you help build will become part of how they verify timing and functional correctness.

What You'll Be Doing

Partner directly with semiconductor companies across the region to solve end-to-end constraint flow challenges including SDC generation, verification, management, and signoff
Deploy and optimize Synopsys constraint tools like Fishtail/TCM, SpyGlass-Constraints, and PrimeTime across customer design flows, working at both RTL and netlist levels
Debug constraint issues, analyze MCP (multi-cycle path), false path, and generated clock reports, and trace problems through RTL, synthesis, and timing signoff
Collaborate with Synopsys R&D and product validation teams to develop methodologies that address customer-specific constraint problems and feed real-world requirements back into product roadmaps
Build and maintain automation scripts in TCL, Perl, and Unix shell to streamline constraint generation, verification, and management workflows
Coordinate with technical account managers and worldwide account teams to shape customer strategies, drive tool adoption, and support successful project completion
Gather, refine, and track flow requirements based on customer feedback, engineering judgment, and emerging tool capabilities, including support for multi-modal analysis and equivalence checks

The Impact You Will Have

Enable semiconductor companies to achieve timing closure faster by solving constraint flow bottlenecks that would otherwise stall projects for weeks or months
Influence the direction of Synopsys constraint verification tools by bringing real customer pain points and use cases directly to R&D teams
Build repeatable, scalable constraint methodologies that become the foundation for how customers manage SDC across multiple projects and product lines
Accelerate customer adoption of Synopsys solutions, directly contributing to business growth and long-term account relationships in the region
Reduce customer design respins by catching constraint errors earlier in the flow, saving significant schedule time and engineering cost
Establish yourself as a trusted technical advisor to design teams, the person they call when constraint verification gets hard
Shape how the next generation of complex, multi-modal chips are constrained and verified, ensuring functional correctness and timing signoff quality

What You'll Need

BE/BTech/ME/MTech in Electronics Engineering, Computer Science, or Microelectronics with 5+ years of hands-on industry experience in ASIC design or verification
End-to-end experience with SDC and constraint flows including constraint generation, verification, management, and signoff
Deep working knowledge of constraint methodologies including multi-cycle paths, false paths, generated clocks, multi-modal analysis, and equivalence checks at RTL and netlist levels
Proven experience with Synopsys constraint tools such as Fishtail/TCM, SpyGlass-Constraints, PrimeTime, or equivalent industry-standard constraint verification and signoff tools
Strong command of VHDL, Verilog, and SystemVerilog RTL, and solid understanding of ASIC design flows from RTL to tapeout
Exposure to timing closure, static timing analysis (STA), and constraint report analysis and debugging
Advanced scripting skills in TCL, Unix shell, Perl, or Python for automation, flow development, and debugging

Who You Are

You can walk into a customer meeting, quickly assess where their constraint flow is breaking down, and propose a concrete next step without needing three follow-up calls
Explaining why a set of constraints is incomplete or incorrect to a design manager or an R&D engineer feels natural to you, and you adjust your explanation depending on who is in the room
You are organized enough to manage multiple customer engagements at once, each with different tools, flows, and timelines, without dropping threads
Working across time zones, teams, and functions does not slow you down, you know how to pull the right people in at the right time and keep things moving
You push back when a customer request does not make technical sense, but you do it in a way that builds trust rather than friction
Debugging a stubborn constraint issue for hours, even days, does not frustrate you, it is the part of the job you actually enjoy

The Team You'll Be Part Of

You will be part of the Application Engineering team supporting Synopsys' constraint verification and management solutions across semiconductor customers in the Bengaluru region. You will work closely with R&D, product validation, technical account managers, and global AE teams to drive methodologies, solve customer problems, and enable successful project outcomes. This is a customer-facing role with deep technical collaboration across the organization.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Constraints Verification Applications Engineer

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