Vacancy description
QUEST BITSILICA SERVICES PRIVATE LIMITED
India, Bengaluru
BITSILICA - DFT Lead Engineer in Bengaluru, India is listed on Jobeax. Browse 30,000+ vacancies available.
Job Title :Senior DFT EngineerAbout the Role :We are seeking a seasoned DFT professional to lead architecture, scan insertion, and compression efforts at both core and SoC levels. The role involves endtoend ATPG pattern generation, coverage analysis, and verification through timing and nontiming simulations, as well as implementation of MemoryBIST solutions. A solid grasp of SSN architecture, clock architecture, and OCC is https://jobeax.com/link/xLduka5Idy6qVDAM Responsibilities :- Design and implement DFT architecture, scan insertion, and compression strategies for core and SoC blocks.- Generate ATPG patterns, perform coverage analysis, and ensure testability goals are met.- Conduct timing and nontiming simulations to validate DFT implementations.- Develop and integrate MemoryBIST schemes across target designs.- Apply knowledge of SSN architecture, clock architecture, and OCC to optimize test structures.- Collaborate with design, verification, and physical teams to resolve DFTrelated issues.- Document DFT methodology, guidelines, and best practices for reuse across https://jobeax.com/link/lYRm4pXQgLMTgQeF Experience :- 8 to 13 years of overall professional experience in semiconductor design.- 8 to 10+ years focused on DFT architecture, scan insertion, and compression at core and SoC levels.- Proven experience with ATPG pattern generation and coverage analysis.- Handson experience with timing and nontiming simulation environments.- Experience implementing MemoryBIST solutions.- Strong understanding of SSN architecture, clock architecture, and OCC https://jobeax.com/link/SKciAM5XjIOOw9Ja Skills :- Familiarity with industrystandard DFT tools (e.g., Synopsys DFT, Mentor Tessent).- Knowledge of lowpower design techniques and their impact on testability.- Experience working in crossfunctional ASIC or SoC development https://jobeax.com/link/tbV87hPFdlI3znrY :- Bachelors degree in Electrical Engineering, Computer Engineering, or a related field.- Demonstrated ability to lead DFT initiatives and mentor junior https://jobeax.com/link/wu2qzfm9XWe4UFnf Summary :- 813 years total experience, with 810+ years in DFT architecture, scan insertion, and compression.- Expertise in ATPG pattern generation, coverage analysis, and both timing and nontiming simulations.- Proven track record delivering MemoryBIST implementations.- Deep knowledge of SSN, clock, and OCC architectures.- Strong collaborative skills across design, verification, and physical teams. (ref:hirist.tech)
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