BITSILICA - Design Verification Manager - SoC/ASIC in Bangalore, भारत

Position Summary :We are seeking an experienced and results-driven Design Verification Manager to lead verification activities for complex IP, subsystem, SoC, and ASIC designs. The ideal candidate will possess strong technical expertise in SystemVerilog/UVM-based verification methodologies, SoC integration, AMBA protocols, and team https://jobeax.com/link/UElKnrRfFoXd0J4r Responsibilities :- Lead and manage Design Verification teams for IP, subsystem, and SoC/ASIC verification projects.- Define verification methodologies, strategies, test plans, coverage goals, and execution timelines.- Drive development of scalable and reusable SystemVerilog/UVM-based verification environments.- Oversee verification of subsystem interfaces, Register Abstraction Layer (RAL), memory subsystems, and protocol compliance.- Guide teams in developing constrained-random, assertion-based, and coverage-driven verification environments.- Ensure successful verification closure including functional coverage, code coverage, assertions, regressions, and debug.- Manage project schedules, resource allocation, priorities, and risk mitigation across multiple concurrent https://jobeax.com/link/CjhPnluynhpzae3L & Experience :- BE/BTech/ME/MTech in Computer Science, Electronics, Electrical Engineering, or related field.- 6 - 12 years of hands-on experience in IP, SoC, or ASIC verification. (ref:hirist.tech)