Category Engineering Hire Type Employee Job ID 19156 Date Posted 10/20/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are an early-career engineer ready to make your mark in semiconductor design. You have spent your academic years drawn to digital design that requires proof, not just simulation. When you see a spec, you think about corner cases and what could break. You have written Verilog or SystemVerilog, debugged logic that did not behave as expected, and you are comfortable in a Unix terminal. Formal verification might be new to you, but the rigor makes sense. You learn by doing, ask questions when stuck, and you do not mind being the person who finds the bug everyone else missed.

What You'll Be Doing

Learn the latest formal verification methodology from experts and apply your learnings to live projects.
Work with a team of seasoned FV engineers and execute validation as per defined plans.
Support quality improvements and contribute insights that help enhance verification tool capabilities.
Write and refine assertions in SystemVerilog Assertions (SVA) to capture design intent and uncover edge-case failures.
Script verification flows using Python, Perl, or Tcl to automate repetitive tasks and improve team productivity in Unix/Linux environments.

The Impact You Will Have

Help catch critical design bugs before tapeout that would otherwise cost months and millions to fix in silicon.
Contribute to the quality and reliability of Synopsys IP and EDA tools that power semiconductor development across the industry.
Accelerate verification closure on complex designs by applying formal methods that simulation alone cannot cover.
Strengthen the formal verification methodology at Synopsys by bringing fresh perspectives and identifying gaps in existing flows.

What You'll Need

Bachelors or Master’s degree in Electronics, Electrical, Instrumentation, or a related engineering discipline
0 to 2 years of experience in digital design, verification, or related semiconductor work (internships, projects, and coursework count).
Strong understanding of computer architecture and digital design fundamentals including state machines, pipelining, and timing.
Hands-on experience with hardware description languages, Verilog or SystemVerilog preferred.
Proficiency in at least one scripting language such as Python, Perl, or Tcl, and comfort working in Unix or Linux environments.
Solid academic performance with relevant coursework or project work in VLSI, digital design, or verification.
Experience with formal verification tools, assertion languages, or model checking is a strong plus.

Who You Are

You can look at a block diagram or RTL code and start asking the right questions about what could go wrong, not just what is supposed to work.
You are comfortable learning new tools and methodologies on the job without needing everything explained upfront, you read documentation, try things, and ask targeted questions when you are stuck.
You communicate clearly when you find something, whether it is a bug, a gap in coverage, or a script that is not working the way it should.
You are detail-oriented enough to track down a single-bit logic error in a complex design without losing sight of what the block is supposed to do.

The Team You'll Be Part Of

You will join a focused team at Synopsys dedicated to advancing formal verification methodologies and delivering proven IP and EDA solutions. You will collaborate with experienced formal verification engineers and design experts who are committed to pushing the boundaries of what formal methods can achieve. The team values rigorous thinking, continuous learning, and clear communication, creating an environment where your growth is supported.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

ASIC Digital Design, Engineer

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