Back to list

Vacancy description

Architect/Lead - Design and Verification - SOC/IP, SystemVerilog/UVM, SOC, RISC-C, Semiconductor Domain in Bangalore, भारत

Career Makers

Bangalore, भारत

About the Role :The role involves building and maintaining scalable testbenches, performing functional verification of complex SoCs and subsystems, and collaborating with cross-functional teams to ensure high-quality silicon. The ideal candidate will have experience with AMBA protocols and power management features https://jobeax.com/link/Q3whGEyCCDNWk1A3 Responsibilities :- Develop and execute verification plans for SoC/IP level designs- Build and maintain scalable testbenches using SystemVerilog/UVM methodology- Perform functional verification of complex SoCs and subsystems- Work on AMBA protocols (AXI/AHB/APB) verification- Verify power management features (PMU, low-power scenarios, UPF-based verification)- Debug simulation failures and root-cause issues efficiently- Collaborate with design, architecture, and validation teams to ensure high-quality silicon- Contribute to coverage closure (functional & code coverage)Required Skills :- Strong background in functional verification- Experience with SystemVerilog/UVM methodology- Knowledge of AMBA protocols (AXI/AHB/APB)- Understanding of power management features (PMU, low-power scenarios, UPF-based verification)Preferred Skills :- Experience with coverage-driven verification- Knowledge of simulation tools and methodologies- Strong debugging and problem-solving skillsQualifications :- Strong technical skills and attention to detail- Ability to work in a team environment and collaborate with cross-functional teams- Good communication and interpersonal skillsBenefits :- Opportunity to work on complex SoC/IP level designs- Collaborative team environment- Professional development opportunitiesInterview Process :- Initial screening of resumes and cover letters- Technical interview with the verification team- Final interview with the hiring managerRecruiter Summary in 5 concise bullets :- Develop and execute verification plans for SoC/IP level designs- Build and maintain scalable testbenches using SystemVerilog/UVM methodology- Perform functional verification of complex SoCs and subsystems- Collaborate with cross-functional teams to ensure high-quality silicon- Contribute to coverage closure and debug simulation failures efficiently (ref:hirist.tech)

Apply to vacancy

Similar vacancies

More like this role

Wipro

Design Verification Architect

... architect scalable UVM environments for subsystem and SoC designs owning coverage closure and verification signoff. What You Will Do - Define the end-to-end verification strategy plans coverage models and signoff criteria. - Architect reusable scalable SystemVerilog/UVM testbenches and VIP at subsystem and SoC level. - Drive ...

Bangalore, भारत

GreenWave Radios™

Lead Engineer Design Verification

... expertise in constrained-random verification, functional and code coverage, assertion-based verification, gate-level simulation (GLS), and reference-model-based verification. - Proven expertise in developing and verifying IPs, subsystem, and SoC-level designs using SystemVerilog, C/C++ and UVM. - Strong hands-on experience integrating ...

Bangalore, भारत

Micron

Design Verification Engineer

  • Full-time
... advance faster than ever. - Own and execute functional verification for block‑level and full‑chip designs from specification through tape‑out - Develop, execute, and maintain verification plans , test strategies, and coverage models based on design specifications - Architect, develop, and maintain SystemVerilog / UVM‑based ...

Hyderabad, भारत

SiFive

Staff Design Verification

  • Full-time
... hands‑on ASIC/SoC/IP design verification experience. - Significant experience verifying out‑of‑order or superscalar CPU cores or similarly complex execution pipelines. - Technical Skills : - Strong proficiency in SystemVerilog and UVM (or equivalent class‑based methodology). - Deep understanding of CPU micro‑architecture, ...

Hyderabad, भारत

SiFive

Senior Design Verification Infrastructure Engineer - VIPs and Testbench

  • Full-time
... the Design Verification and other verification and validation teams on best practices and how to achieve them with the Verification Platform Requirements: - Design Verification experience with System Verilog and UVM - Experience designing and verifying VIPs, AIPs, and other testbench components - Understanding of modern ...

Bangalore, भारत

SiFive

Staff Design Verification Infrastructure Engineer - VIPs and Testbench

  • Full-time
... the Design Verification and other verification and validation teams on best practices and how to achieve them with the Verification Platform Requirements: - Design Verification experience with System Verilog and UVM - Experience designing and verifying VIPs, AIPs, and other testbench components - Understanding of modern ...

Bangalore, भारत

EdgeCortix

[India] Design Verification Engineer

  • Remote
  • Full-time
... Working closely with the design architecture team and contributing to IP, performance and SoC related verification - Writing configurable testbenches in SystemVerilog/UVM and testbench automation - Writing System verilog assertions and maintaining them What you need - Verilog - UVM - Computer vision Good to have - Python ...

Hyderabad, भारत

Renesas Electronics

Sr Engineer, Design Verification

  • Full-time
... a must. Responsibilities: - Develop verification testbench components for chip/module level using System Verilog. - Use high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment. - Define and execute detailed verification plan from spec working with architects and designer engineers - Experience ...

Bangalore, भारत

Semtech

Staff Verification Design Engineer

  • Full-time
... EE/CS/CE or higher - Hands-on experience with System Verilog as High-level Verification Language and UVM implementation. - Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level. - Scripting experience in Python or Perl. - Clear understanding of ASIC design flow - Solid ...

Hyderabad, भारत

SiFive

Staff Design Verification Engineer

  • Full-time
... ASIC/SoC/IP design verification , with significant experience on out‑of‑order CPU or advanced core projects. Technical Skills - Strong expertise in System Verilog and UVM . - Direct verification experience with OOO CPU micro‑architecture , including several of: - Instruction fetch, decode, rename, and register mapping. - Issue ...

Hyderabad, भारत