ACL Digital - Design Verification Engineer - System Verilog/UVM in Hyderabad, भारत

Role : Design Verification EngineerACL Digital is seeking a Design Verification Engineer with hands-on experience in SystemVerilog and UVM-based verification. The role involves developing block/IP-level testbenches, executing verification plans, managing regressions, and performing real-number modeling and Gate-Level Simulation (GLS).Key Responsibilities : - Develop and maintain block/IP-level testbenches using SystemVerilog and UVM.- Execute verification plans (Vplan) and track verification progress.- Manage regression runs and analyze verification results.- Work on real-number modeling for design verification.- Perform Gate-Level Simulations (GLS).- Support subsystem and SoC-level verification activities, where https://jobeax.com/link/g3fodVl7LLxPdvXs Skills : - 3+ years of experience in design verification.- Strong knowledge of SystemVerilog and UVM.- Experience in block/IP-level testbench development and Vplan execution.- Hands-on experience with regression management, real-number modeling, and GLS.- Subsystem/SoC verification experience is an added advantage.- Ability to join within 0 - 30 days (ref:hirist.tech)