ACL Digital - Design Verification Engineer - System Verilog/UVM in Hyderabad, भारत
ALTEN CALSOFT LABS (INDIA) PRIVATE LIMITED
Hyderabad, भारत
Role : Design Verification EngineerACL Digital is seeking a Design Verification Engineer with hands-on experience in SystemVerilog and UVM-based verification. The role involves developing block/IP-level testbenches, executing verification plans, managing regressions, and performing real-number modeling and Gate-Level Simulation (GLS).Key Responsibilities : - Develop and maintain block/IP-level testbenches using SystemVerilog and UVM.- Execute verification plans (Vplan) and track verification progress.- Manage regression runs and analyze verification results.- Work on real-number modeling for design verification.- Perform Gate-Level Simulations (GLS).- Support subsystem and SoC-level verification activities, where https://jobeax.com/link/g3fodVl7LLxPdvXs Skills : - 3+ years of experience in design verification.- Strong knowledge of SystemVerilog and UVM.- Experience in block/IP-level testbench development and Vplan execution.- Hands-on experience with regression management, real-number modeling, and GLS.- Subsystem/SoC verification experience is an added advantage.- Ability to join within 0 - 30 days (ref:hirist.tech)
Verification / Firmware EngineerACL Digital is looking for an experienced Verification / Firmware Engineer to contribute to large-scale ASIC development https://jobeax.com/link/kS6lr8ikjUi7EbPN role focuses on software-driven verification, firmware development, system-level debugging, and validation of hardware functionality ...
Role : Physical Design EngineerACL Digital is looking for a Physical Design Engineer to lead end-to-end RTL-to-GDSII execution for high-performance FinFET ASICs across 16nm - 5nm and dual-patterning technology nodes. The role focuses on physical implementation, timing and power optimization, physical verification, and automated ...
... preferably in automotive semiconductor development.- https://jobeax.com/link/2DENLGgQM7whDhaE or https://jobeax.com/link/s1WvHFV9ITSwCkyS in Electronics, Electrical Engineering, VLSI, or a related discipline.- Strong hands-on experience with Verilog and SystemVerilog.- Understanding of digital design principles and RTL coding practices.- ...
... and SoC projects across global teams * Define, document, and propagate verification methodologies and best practices that become the standard across Synopsys digital IP projects * Lead and mentor verification engineers, providing technical guidance on UVM, SystemVerilog, flow optimization, and debugging strategies * Drive ...
... SCAN DRC, coverage debugging, and ATPG pattern generation.- Experience with zero-delay and timing-delay gate-level simulations.- Knowledge of JTAG and P1500 protocols.- Proficiency in Perl/Tcl scripting.- Knowledge of timing, formal verification, or physical design (PD) flows is an added advantage (ref:hirist.tech) []
... closely with design, and verification engineering. - In addition, strong collaboration and communication skills are a must. Duties/Responsibilities: - Develop verification testbench components for chip/module level using System Verilog. - Use high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment. ...
Design Verification - Job Description: We are seeking a skilled Design Verification Engineer with hands-on experience in live projects. If you have a passion for developing functional verification environments, excellent debugging skills, and a collaborative mindset, we invite you to join our dynamic team in Bangalore/Kochi/Chennai/Pune. ...
Meta is hiring for the role of ASIC Engineer Intern, Design Verification! Responsibilities of the Intern: - Develop tests, checkers and coverage to help verify designs. - Develop understanding of the architecture and microarchitecture of designs. - SystemVerilog/UVM/C code to generate test content. - Develop scripts to ...
... Chennai / PuneJob Type : Full-timeAbout the Role : We are looking for a skilled Design Verification Engineer with hands-on experience in live semiconductor/SoC verification projects. The ideal candidate should have strong expertise in SystemVerilog and UVM, functional verification methodologies, protocol verification, and https://jobeax.com/link/Fhfpw3PcjAdqTGJR ...
... Electronics Engineering, Electrical Engineering or a related discipline. - 6 - 14 years of experience in Digital Verification with Strong expertise in System Verilog, UVM methodology and constrained-random verification. - Experience with Formal Verification techniques and tools to complement simulation-based verification - advantage. ...