ACL Digital - Design Verification Engineer - System Verilog/UVM in Hyderabad, भारत
ALTEN CALSOFT LABS (INDIA) PRIVATE LIMITED
Hyderabad, भारत
Role : Design Verification EngineerACL Digital is seeking a Design Verification Engineer with hands-on experience in SystemVerilog and UVM-based verification. The role involves developing block/IP-level testbenches, executing verification plans, managing regressions, and performing real-number modeling and Gate-Level Simulation (GLS).Key Responsibilities : - Develop and maintain block/IP-level testbenches using SystemVerilog and UVM.- Execute verification plans (Vplan) and track verification progress.- Manage regression runs and analyze verification results.- Work on real-number modeling for design verification.- Perform Gate-Level Simulations (GLS).- Support subsystem and SoC-level verification activities, where https://jobeax.com/link/g3fodVl7LLxPdvXs Skills : - 3+ years of experience in design verification.- Strong knowledge of SystemVerilog and UVM.- Experience in block/IP-level testbench development and Vplan execution.- Hands-on experience with regression management, real-number modeling, and GLS.- Subsystem/SoC verification experience is an added advantage.- Ability to join within 0 - 30 days (ref:hirist.tech)
... design timing requirements and ECO closure.- Coordinate cross-functional sign-off activities to ensure successful tape-outs.- Mentor junior layout and timing engineers throughout the design and sign-off https://jobeax.com/link/f58guS2D0eJLGatP Skills :- 13+ years of experience in STA and physical design.- Deep expertise in ...
... ever. - Own and execute functional verification for block‑level and full‑chip designs from specification through tape‑out - Develop, execute, and maintain verification plans , test strategies, and coverage models based on design specifications - Architect, develop, and maintain SystemVerilog / UVM‑based testbenches , test ...
... do - Working closely with the design architecture team and contributing to IP, performance and SoC related verification - Writing configurable testbenches in SystemVerilog/UVM and testbench automation - Writing System verilog assertions and maintaining them What you need - Verilog - UVM - Computer vision Good to have - Python ...
... work closely with design, and verification engineering. - In addition, strong collaboration and communication skills are a must. Responsibilities: - Develop verification testbench components for chip/module level using System Verilog. - Use high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment. ...
... Minimum Qualifications: - 3+ years experience in semiconductor industry - M.S. in EE/CS/CE or higher - Hands-on experience with System Verilog as High-level Verification Language and UVM implementation. - Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level. - Scripting ...
... years in ASIC/SoC/IP design verification , with significant experience on out‑of‑order CPU or advanced core projects. Technical Skills - Strong expertise in System Verilog and UVM . - Direct verification experience with OOO CPU micro‑architecture , including several of: - Instruction fetch, decode, rename, and register ...
... BFM, agents, monitor, scoreboard, checkers et al and 3rd party VIP integration. - Proficient in coding Pre-Silicon functional verifications tests to verify design to meet spec. requirements. - Creates efficient test plans for RTL validation and Gate level simulations. - Expertise in System Verilog, UVM, and/or OVM based ...
... industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, ...
... more years of relevant digital design verification experience, or equivalent directly applicable experience. - Demonstrated ownership of a complex block, subsystem, or major feature from verification planning through closure. - Strong proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, ...