ACL Digital - Design Verification Engineer - System Verilog/UVM in Hyderabad, भारत
ALTEN CALSOFT LABS (INDIA) PRIVATE LIMITED
Hyderabad, भारत
Role : Design Verification EngineerACL Digital is seeking a Design Verification Engineer with hands-on experience in SystemVerilog and UVM-based verification. The role involves developing block/IP-level testbenches, executing verification plans, managing regressions, and performing real-number modeling and Gate-Level Simulation (GLS).Key Responsibilities : - Develop and maintain block/IP-level testbenches using SystemVerilog and UVM.- Execute verification plans (Vplan) and track verification progress.- Manage regression runs and analyze verification results.- Work on real-number modeling for design verification.- Perform Gate-Level Simulations (GLS).- Support subsystem and SoC-level verification activities, where https://jobeax.com/link/g3fodVl7LLxPdvXs Skills : - 3+ years of experience in design verification.- Strong knowledge of SystemVerilog and UVM.- Experience in block/IP-level testbench development and Vplan execution.- Hands-on experience with regression management, real-number modeling, and GLS.- Subsystem/SoC verification experience is an added advantage.- Ability to join within 0 - 30 days (ref:hirist.tech)
Verification / Firmware EngineerACL Digital is looking for an experienced Verification / Firmware Engineer to contribute to large-scale ASIC development https://jobeax.com/link/kS6lr8ikjUi7EbPN role focuses on software-driven verification, firmware development, system-level debugging, and validation of hardware functionality ...
Role : Physical Design EngineerACL Digital is looking for a Physical Design Engineer to lead end-to-end RTL-to-GDSII execution for high-performance FinFET ASICs across 16nm - 5nm and dual-patterning technology nodes. The role focuses on physical implementation, timing and power optimization, physical verification, and automated ...
... preferably in automotive semiconductor development.- https://jobeax.com/link/2DENLGgQM7whDhaE or https://jobeax.com/link/s1WvHFV9ITSwCkyS in Electronics, Electrical Engineering, VLSI, or a related discipline.- Strong hands-on experience with Verilog and SystemVerilog.- Understanding of digital design principles and RTL coding practices.- ...
... and SoC projects across global teams * Define, document, and propagate verification methodologies and best practices that become the standard across Synopsys digital IP projects * Lead and mentor verification engineers, providing technical guidance on UVM, SystemVerilog, flow optimization, and debugging strategies * Drive ...
... SCAN DRC, coverage debugging, and ATPG pattern generation.- Experience with zero-delay and timing-delay gate-level simulations.- Knowledge of JTAG and P1500 protocols.- Proficiency in Perl/Tcl scripting.- Knowledge of timing, formal verification, or physical design (PD) flows is an added advantage (ref:hirist.tech) []
... ever. - Own and execute functional verification for block‑level and full‑chip designs from specification through tape‑out - Develop, execute, and maintain verification plans , test strategies, and coverage models based on design specifications - Architect, develop, and maintain SystemVerilog / UVM‑based testbenches , test ...
... Minimum Qualifications: - 3+ years experience in semiconductor industry - M.S. in EE/CS/CE or higher - Hands-on experience with System Verilog as High-level Verification Language and UVM implementation. - Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level. - Scripting ...
... years in ASIC/SoC/IP design verification , with significant experience on out‑of‑order CPU or advanced core projects. Technical Skills - Strong expertise in System Verilog and UVM . - Direct verification experience with OOO CPU micro‑architecture , including several of: - Instruction fetch, decode, rename, and register ...
... BFM, agents, monitor, scoreboard, checkers et al and 3rd party VIP integration. - Proficient in coding Pre-Silicon functional verifications tests to verify design to meet spec. requirements. - Creates efficient test plans for RTL validation and Gate level simulations. - Expertise in System Verilog, UVM, and/or OVM based ...